作者
Nadim Chowdhury, Jaeyoung Jung, Qingyun Xie, Mengyang Yuan, Kai Cheng, Tomás Palacios
发表日期
2021/6/20
研讨会论文
2021 Device Research Conference (DRC)
页码范围
1-2
出版商
IEEE
简介
The performance of GaN CMOS technology was systematically evaluated through experimentally calibrated simulations. Logic inverters based on self-aligned p-FETs and n-FinFETs with W p /W n =5 exhibit 1.4 V of logic-low noise margin (NML) and 2.8 V of high noise margin (NMH) for V DD =5 V. Simulations also confirmed that GaN CMOS logic building blocks are operational with negligible performance degradation at high temperature (300 °C).
学术搜索中的文章
N Chowdhury, J Jung, Q Xie, M Yuan, K Cheng… - 2021 Device Research Conference (DRC), 2021