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FPGAs have become a popular choice for deploying Convolutional Neural Networks (CNNs). As a result, many researchers have explored the deployment and mapping of CNN on FPGA. However, the verification of these deployments at the design time is one of the biggest challenges. The need for design-time verification is growing exponentially because of its use in safety-critical applications. To the best of our knowledge, this is the first work that proposes a 2-Level 3-Way (2L-3W) hardware–software co-verification methodology at design time. 2L-3W provides a step-by-step guide for the successful mapping, deployment, and verification of CNN on FPGA boards. The 2-Level verification serves the purpose of ensuring the implementation in each stage (software and hardware) is following the desired behavior. The 3-Way co-verification provides a cross-paradigm (software, design architecture, and …