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Convolutional Neural Networks (CNN) have shown impressive performance in computer vision, natural language processing, and many other applications, but they exhibit high computations and substantial memory requirements. To address these limitations, the use of cloud computing for CNNs is becoming more popular. This comes with privacy and latency concerns that have motivated the designers to develop embedded hardware accelerators for CNNs. Hardware accelerators on FPGAs have become a popular choice for deploying Convolutional Neural Network (CNN). In literature, researchers have explored the deployment and mapping of CNN on FPGA, but there has been a growing need to do design-time hardware-software co-verification of these deployments. One of the first goals of this dissertation is to investigate a 2-Level 3-Way (2L-3W) hardware-software co-verification methodology and provide a …