作者
Chao Chen, Zhao Chen, Deep Bera, Shreyas B Raghunathan, Maysam Shabanimotlagh, Emile Noothout, Zu-Yao Chang, Jacco Ponte, Christian Prins, Hendrik J Vos, Johan G Bosch, Martin D Verweij, Nico De Jong, Michiel AP Pertijs
发表日期
2017/1/5
期刊
IEEE Journal of Solid-State Circuits
卷号
52
期号
4
页码范围
994-1006
出版商
IEEE
简介
This paper presents a power- and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography. The 6.1 × 6.1 mm 2 ASIC, implemented in a low-voltage 0.18-μm CMOS process, effectively reduces the number of receive (RX) cables required in the probe's narrow shaft by ninefold with the aid of 96 delay-and-sum beamformers, each of which locally combines the signals received by a sub-array of 3 × 3 elements. These beamformers are based on pipeline-operated analog sample-and-hold stages and employ a mismatch-scrambling technique to prevent the ripple signal associated with the mismatch between these stages from limiting the dynamic range. In addition, an ultralow-power low-noise amplifier architecture is …
引用总数
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