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A novel analogue CMOS design of a cortical cell, that computes weighted sum of inputs, is presented. The cell’s feedback regime exploits the adaptation dynamics of floating gate p FET ‘synapse’to perform competitive learning amongst input weights as time-staggered winner take all. A learning rate parameter regulates adaptation time and a bias enforces resource limitation by restricting the number of input branches and winners in a competition. When learning ends, the cell’s response favours one input pattern over others to exhibit feature selectivity. Embedded in a 2-D RC grid, these feature selective cells are capable of performing a symmetry breaking pattern formation, observed in some reaction–diffusion models of cortical feature map formation, eg ocular dominance. Close similarity with biological networks in terms of adaptability and long term memory indicates that the cell’s design is ideally suited for …