作者
Alessandro Cevrero, Cosimo Aprile, Pier Andrea Francese, Urs Bapst, Christian Menolfi, Matthias Braendli, Marcel Kossel, Thomas Morf, Lukas Kull, Hazar Yueksel, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl
发表日期
2015/6/17
研讨会论文
2015 Symposium on VLSI Circuits (VLSI Circuits)
页码范围
C228-C229
出版商
IEEE
简介
This work reports an 8-lane single-ended RX featuring compact and low power far-end crosstalk (FEXT) cancellation circuits. The RX data-path consists of a cross continuous-time linear equalizer (XCTLE) to remove FEXT by nearest aggressors within the channel bundle. Residual post-cursor FEXT is suppressed by a direct feedback 7×8-tap cross decision-feedback equalizer (XDFE). A CTLE and 8-tap DFE equalize single-ended channels with 28dB insertion loss at Nyquist frequency without TX FFE. The circuit, fabricated in 32nm SOI CMOS, was measured to receive 7Gb/s/pin PRBS11 data at BER<; 10 -12 with 12.5%UI margin. Itoccupies 300×350μm 2 with an energy efficiency of 5.9mW/Gb/s.
引用总数
20152016201720182019202020212022132412
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