作者
Ahmed Alhammad, Saud Wasly, Rodolfo Pellizzoni
发表日期
2015/4/13
研讨会论文
21st IEEE Real-Time and Embedded Technology and Applications Symposium
页码范围
285-296
出版商
IEEE
简介
Current computing architectures are commonly built with multiple cores and a single shared main memory. Even though this architecture increases the overall computation power, main memory can easily become a bottleneck. Simultaneous access to main memory from multiple cores can cause both (1) severe degradation in performance and (2) unpredictable execution time for real-time applications. We propose in this paper to mitigate these two problems by co-scheduling cores as well as the main memory for predictable execution. In particular, we use a DMA component to overlap memory with computation for hiding the memory latency and therefore increasing the system performance. The main contribution of this paper is a novel global co-scheduling algorithm along with its associated schedulability analysis for sporadic hard real-time tasks. We evaluated our system by generating synthetic tasksets based on …
引用总数
2015201620172018201920202021202220232024367111279832
学术搜索中的文章
A Alhammad, S Wasly, R Pellizzoni - 21st IEEE Real-Time and Embedded Technology and …, 2015