Systematic poisoning attacks on and defenses for machine learning in healthcare M Mozaffari-Kermani, S Sur-Kolay, A Raghunathan, NK Jha IEEE journal of biomedical and health informatics 19 (6), 1893-1905, 2014 | 282 | 2014 |
Wearable medical sensor-based system design: A survey A Mosenia, S Sur-Kolay, A Raghunathan, NK Jha IEEE Transactions on Multi-Scale Computing Systems 3 (2), 124-138, 2017 | 157 | 2017 |
Energy-efficient long-term continuous personal health monitoring AM Nia, M Mozaffari-Kermani, S Sur-Kolay, A Raghunathan, NK Jha IEEE Transactions on Multi-Scale Computing Systems 1 (2), 85-98, 2015 | 133 | 2015 |
A modeling approach for addressing power supply switching noise related failures of integrated circuits C Tirumurti, S Kundu, S Sur-Kolay, YS Chang Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 99 | 2004 |
CABA: Continuous authentication based on BioAura A Mosenia, S Sur-Kolay, A Raghunathan, NK Jha IEEE Transactions on Computers 66 (5), 759-772, 2016 | 82 | 2016 |
PAQCS: Physical design-aware fault-tolerant quantum circuit synthesis CC Lin, S Sur-Kolay, NK Jha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (7 …, 2014 | 76 | 2014 |
Routing of L-shaped channels, switchboxes and staircases in manhattan-diagonal model S Das, S Sur-Kolay, BB Bhattacharya Proceedings Eleventh International Conference on VLSI Design, 65-70, 1998 | 70 | 1998 |
Linear nearest neighbor synthesis of reversible circuits by graph partitioning A Chakrabarti, S Sur-Kolay, A Chaudhury arXiv preprint arXiv:1112.0564, 2011 | 63 | 2011 |
Floorplanning for partially reconfigurable FPGAs P Banerjee, M Sangtani, S Sur-Kolay IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 63 | 2010 |
Physiological information leakage: A new frontier in health information security AM Nia, S Sur-Kolay, A Raghunathan, NK Jha IEEE Transactions on Emerging Topics in Computing 4 (3), 321-334, 2015 | 62 | 2015 |
Secure public verification of IP marks in FPGA design through a zero-knowledge protocol D Saha, S Sur-Kolay IEEE transactions on very large scale integration (VLSI) systems 20 (10 …, 2011 | 45 | 2011 |
Nearest neighbour based synthesis of quantum boolean circuits A Chakrabarty, S Sur Kolay | 43 | 2007 |
Synthesis techniques for ternary quantum logic SB Mandal, A Chakrabarti, S Sur-Kolay 2011 41st IEEE International Symposium on Multiple-Valued Logic, 218-223, 2011 | 33 | 2011 |
Fast unified floorplan topology generation and sizing on heterogeneous FPGAs P Banerjee, S Sur-Kolay, A Bishnu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009 | 33 | 2009 |
Fundamentals of IP and SoC security S Bhunia, S Ray, S Sur-Kolay Springer, 2017 | 31 | 2017 |
SoC: a real platform for IP reuse, IP infringement, and IP protection D Saha, S Sur-Kolay VLSI Design 2011 (1), 731957, 2011 | 27 | 2011 |
Combined instruction and loop parallelism in array synthesis for FPGAs S Derrien, S Rajopadhye, SS Kolay Proceedings of the 14th international symposium on Systems Synthesis, 165-170, 2001 | 27 | 2001 |
The cycle structure of channel graphs in nonsliceable floorplans and a unified algorithm for feasible routing order S Sur-Kolay, BB Bhattacharya 1991 IEEE International Conference on Computer Design: VLSI in Computers and …, 1991 | 27 | 1991 |
Optimizing ansatz design in QAOA for Max-cut R Majumdar, D Madan, D Bhoumik, D Vinayagamurthy, S Raghunathan, ... arXiv preprint arXiv:2106.02812, 2021 | 26 | 2021 |
Approximation algorithms for maximum independent set of a unit disk graph GK Das, M De, S Kolay, SC Nandy, S Sur-Kolay Information Processing Letters 115 (3), 439-446, 2015 | 24 | 2015 |