| Advances in logic locking: Past, present, and prospects HM Kamali, KZ Azar, F Farahmandi, M Tehranipoor Cryptology ePrint Archive, 2022 | 99 | 2022 |
| Defense-in-depth: A recipe for logic locking to prevail MT Rahman, MS Rahman, H Wang, S Tajik, W Khalil, F Farahmandi, ... Integration 72, 39-57, 2020 | 96 | 2020 |
| Pre-silicon security verification and validation: A formal perspective X Guo, RG Dutta, Y Jin, F Farahmandi, P Mishra Proceedings of the 52nd annual design automation conference, 1-6, 2015 | 93 | 2015 |
| Hardware Trojan detection using ATPG and model checking J Cruz, F Farahmandi, A Ahmed, P Mishra 2018 31st international conference on VLSI design and 2018 17th …, 2018 | 86 | 2018 |
| System-on-chip security F Farahmandi, Y Huang, P Mishra Cham, Switzerland: Springer, 2020 | 75 | 2020 |
| Trojan localization using symbolic algebra F Farahmandi, Y Huang, P Mishra 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 591-597, 2017 | 69 | 2017 |
| Security-aware FSM design flow for identifying and mitigating vulnerabilities to fault attacks A Nahiyan, F Farahmandi, P Mishra, D Forte, M Tehranipoor IEEE Transactions on Computer-aided design of integrated circuits and …, 2018 | 66 | 2018 |
| Gröbner basis based formal verification of large arithmetic circuits using gaussian elimination and cone-based polynomial extraction F Farahmandi, B Alizadeh Microprocessors and Microsystems 39 (2), 83-96, 2015 | 61 | 2015 |
| Scalable hardware trojan activation by interleaving concrete simulation and symbolic execution A Ahmed, F Farahmandi, Y Iskander, P Mishra 2018 IEEE International Test Conference (ITC), 1-10, 2018 | 56 | 2018 |
| Directed test generation using concolic testing on RTL models A Ahmed, F Farahmandi, P Mishra 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 53 | 2018 |
| Sofi: Security property-driven vulnerability assessments of ics against fault-injection attacks H Wang, H Li, F Rahman, MM Tehranipoor, F Farahmandi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 47 | 2021 |
| Soc security verification using property checking N Farzana, F Rahman, M Tehranipoor, F Farahmandi 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 47 | 2019 |
| Automated Test Generation for Debugging Arithmetic Circuits F Farahmandi, P Mishra Design Automation and Test in Europe (DATE), 2016 | 46 | 2016 |
| Security assessment of dynamically obfuscated scan chain against oracle-guided attacks MS Rahman, A Nahiyan, F Rahman, S Fazzari, K Plaks, F Farahmandi, ... ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (4 …, 2021 | 39 | 2021 |
| Script: A cad framework for power side-channel vulnerability assessment using information flow tracking and pattern generation A Nahiyan, J Park, M He, Y Iskander, F Farahmandi, D Forte, ... ACM Transactions on Design Automation of Electronic Systems (TODAES) 25 (3 …, 2020 | 39 | 2020 |
| FPGA bitstream security: a day in the life A Duncan, F Rahman, A Lukefahr, F Farahmandi, M Tehranipoor 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 39 | 2019 |
| eChain: A blockchain-enabled ecosystem for electronic device authenticity verification N Vashistha, MM Hossain, MR Shahriar, F Farahmandi, F Rahman, ... IEEE Transactions on Consumer Electronics 68 (1), 23-37, 2021 | 38 | 2021 |
| Automated test generation for debugging multiple bugs in arithmetic circuits F Farahmandi, P Mishra IEEE Transactions on Computers 68 (2), 182-197, 2018 | 36 | 2018 |
| PSC-TG: RTL power side-channel leakage assessment with test pattern generation T Zhang, J Park, M Tehranipoor, F Farahmandi 2021 58th ACM/IEEE Design Automation Conference (DAC), 709-714, 2021 | 35 | 2021 |
| Cost-effective analysis of post-silicon functional coverage events F Farahmandi, R Morad, A Ziv, Z Nevo, P Mishra Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 34 | 2017 |
Mark M. TehranipoorIntel Charles E. Young Endowed Chair Professor, ECE, University of Florida在 ufl.edu 的电子邮件经过验证
