| A triple core lock-step (tcls) arm® cortex®-r5 processor for safety-critical and ultra-reliable applications X Iturbe, B Venu, E Ozer, S Das 2016 46th Annual IEEE/IFIP International Conference on Dependable Systems …, 2016 | 80 | 2016 |
| Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU X Iturbe, B Venu, E Ozer 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2016 | 53 | 2016 |
| Multi-core processors-an overview B Venu arXiv preprint arXiv:1110.3535, 2011 | 51 | 2011 |
| The Arm triple core lock-step (TCLS) processor X Iturbe, B Venu, E Ozer, JL Poupat, G Gimenez, HU Zurek ACM Transactions on Computer Systems (TOCS) 36 (3), 1-30, 2019 | 46 | 2019 |
| Addressing functional safety challenges in autonomous vehicles with the arm TCL S architecture X Iturbe, B Venu, J Jagst, E Ozer, P Harrod, C Turner, J Penton IEEE Design & Test 35 (3), 7-14, 2018 | 38 | 2018 |
| Device, system and process for redundant processor error detection E Ozer, X Iturbe, V Balaji US Patent 10,628,277, 2020 | 12 | 2020 |
| Error correlation prediction in lockstep processors for safety-critical systems E Ozer, B Venu, X Iturbe, S Das, S Lyberis, J Biggs, P Harrod, J Penton 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 10 | 2018 |
| A triple core lock-step ARM Cortex-R5 processor for safety-critical and ultra-reliable applications X Iturbe, B Venu, E Ozer, S Das IEEE DSN, 2016 | 10 | 2016 |
| Industrial challenge 2022: A high-performance real-time case study on arm M Andreozzi, G Gabrielli, B Venu, G Travaglini 34th Euromicro Conference on Real-Time Systems (ECRTS 2022), 2022 | 9 | 2022 |
| A fail-functional automotive CPU subsystem architecture for mitigating single point of failures B Venu, E Ozer, X Iturbe, A Robinson IEEE International Workshop on Automotive Reliability and Test, 2017 | 7 | 2017 |
| Self-testing in a processor core V Balaji, KY Johar, M Bonino US Patent 10,331,531, 2019 | 5 | 2019 |
| A" high resilience" mode to minimize soft error vulnerabilities in ARM cortex-R CPU pipelines: work-in-progress X Iturbe, B Venu, J Penton, E Ozer Proceedings of the 2017 International Conference on Compilers, Architectures …, 2017 | 5 | 2017 |
| Error protection E Özer, V Balaji US Patent 10,108,486, 2018 | 4 | 2018 |
| Formal verification methodology considerations for network on chips B Venu, A Singh Proceedings of the International Conference on Advances in Computing …, 2012 | 4 | 2012 |
| An Exploration of Microprocessor Self-Test Optimisation Based On Safe Faults A Narang, B Venu, S Khursheed, P Harrod 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2021 | 3 | 2021 |
| Handling errors in buffers V Balaji, ML Boettcher, M Eyole US Patent 11,113,164, 2021 | 3 | 2021 |
| Apparatus and method for checking output data during redundant execution of instructions E Özer, V Balaji, X Iturbe, AJ Penton US Patent 10,303,566, 2019 | 3 | 2019 |
| Targeted recovery process V Balaji, X Iturbe, E Özer US Patent 10,185,635, 2019 | 3 | 2019 |
| FPGA based low complexity multipurpose reconfigurable image processor V Balaji, R Krishnaveni International Conference on Information Communication and Embedded Systems …, 2014 | 3 | 2014 |
| Apparatus and method for increasing resilience to faults X Iturbe, E Özer, V Balaji, AJ Penton US Patent 10,289,332, 2019 | 2 | 2019 |
