| A 0.65-V 12–16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and −256.4-dB FoM Z Zhang, G Zhu, CP Yue IEEE Journal of Solid-State Circuits 55 (6), 1665-1683, 2020 | 77 | 2020 |
| A 2.4–3.6-GHz wideband subharmonically injection-locked PLL with adaptive injection timing alignment technique Z Zhang, L Liu, P Feng, N Wu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3), 929-941, 2016 | 31 | 2016 |
| A 50-Gb/s PAM-4 silicon-photonic transmitter incorporating lumped-segment MZM, distributed CMOS driver, and integrated CDR Q Liao, Y Zhang, S Ma, L Wang, L Li, G Li, Z Zhang, J Liu, N Wu, L Liu, ... IEEE Journal of Solid-State Circuits 57 (3), 767-780, 2021 | 30 | 2021 |
| A 0.9–2.25-GHz sub-0.2-mW/GHz compact low-voltage low-power hybrid digital PLL with loop bandwidth-tracking technique Z Zhang, J Yang, L Liu, P Feng, J Liu, N Wu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (5), 933-944, 2018 | 29 | 2018 |
| Source‐switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL Z Zhang, J Yang, L Liu, P Feng, J Liu, N Wu Electronics Letters 52 (14), 1211-1212, 2016 | 27 | 2016 |
| Trending IC design directions in 2022 CH Chan, L Cheng, W Deng, P Feng, L Geng, M Huang, H Jia, L Jie, ... Journal of Semiconductors 43 (7), 071401, 2022 | 24 | 2022 |
| A 32-Gb/s 0.46-pJ/bit PAM4 CDR using a quarter-rate linear phase detector and a self-biased PLL-based multiphase clock generator Z Zhang, G Zhu, C Wang, L Wang, CP Yue IEEE Journal of Solid-State Circuits 55 (10), 2734-2746, 2020 | 22 | 2020 |
| A 15-Gb/s 0.0037-mm² 0.019-pJ/bit full-rate programmable multi-pattern pseudo-random binary sequence generator J Hu, Z Zhang, Q Pan IEEE Transactions on Circuits and Systems II: Express Briefs 67 (9), 1499-1503, 2020 | 20 | 2020 |
| An 18–23 GHz 57.4-fs RMS jitter− 253.5-dB FoM sub-harmonically injection-locked all-digital PLL with single-ended injection technique and ILFD aided adaptive injection timing … Z Zhang, J Yang, L Liu, N Qi, P Feng, J Liu, N Wu IEEE Transactions on Circuits and Systems I: Regular Papers 66 (10), 3733-3746, 2019 | 16 | 2019 |
| Design of a PAM-4 VCSEL-based transceiver front-end for beyond-400G short-reach optical interconnects J He, D Lu, H Xue, S Chen, H Liu, L Li, G Li, Z Zhang, J Liu, L Liu, N Wu, ... IEEE Transactions on Circuits and Systems I: Regular Papers 69 (11), 4345-4357, 2022 | 15 | 2022 |
| Terahertz detector for imaging in 180-nm standard CMOS process Z Liu, L Liu, Z Zhang, J Liu, N Wu Science China Information Sciences 60, 1-9, 2017 | 15 | 2017 |
| A 56-Gb/s reconfigurable silicon-photonics transmitter using high-swing distributed driver and 2-tap in-segment feed-forward equalizer in 65-nm CMOS J He, Y Zhang, H Liu, Q Liao, Z Zhang, M Li, F Jiang, J Shi, J Liu, N Wu, ... IEEE Transactions on Circuits and Systems I: Regular Papers 69 (3), 1159-1170, 2021 | 14 | 2021 |
| A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects C Wang, L Wang, Z Zhang, MK Mahmoudabadi, W Shi, CP Yue IEEE Open Journal of Circuits and Systems 2, 46-55, 2021 | 14 | 2021 |
| A 0.25–0.4-V, sub-0.11-mW/GHz, 0.15–1.6-GHz PLL using an offset dual-path architecture with dynamic charge pumps Z Zhang, G Zhu, CP Yue IEEE Journal of Solid-State Circuits 56 (6), 1871-1885, 2020 | 9 | 2020 |
| A 0.25-0.4 V, sub-0.11 mW/GHz, 0.15-1.6 GHz PLL using an offset dual-path loop architecture with dynamic charge pumps Z Zhang, G Zhu, CP Yue 2019 Symposium on VLSI Circuits, C158-C159, 2019 | 9 | 2019 |
| CMOS analog and mixed-signal phase-locked loops: An overview Z Zhang Journal of Semiconductors 41 (11), 111402, 2020 | 8 | 2020 |
| A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing Z Zhang, L Liu, N Wu 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 369-372, 2014 | 8 | 2014 |
| 0.1–5 GHz wideband ΔΣ fractional‐N frequency synthesiser for software‐defined radio application Z Zhang, J Yang, L Liu, N Qi, P Feng, J Liu, N Wu IET Circuits, Devices & Systems 13 (7), 1071-1077, 2019 | 7 | 2019 |
| The design techniques for high-speed PAM4 clock and data recovery Q Liao, N Qi, Z Zhang, L Liu, J Liu, N Wu, X Xiao, PY Chiang 2018 IEEE International Conference on Integrated Circuits, Technologies and …, 2018 | 7 | 2018 |
| A fast auto-frequency calibration technique for wideband PLL with wide reference frequency range Z Zhang, J Yang, L Liu, N Qi, P Feng, J Liu, N Wu 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), 227-230, 2018 | 7 | 2018 |
Nanjian WuInstitute of Semiconductors在 red.semi.ac.cn 的电子邮件经过验证
