| A 0.49–13.3 MHz tunable fourth-order LPF with complex poles achieving 28.7 dBm OIP3 P Payandehnia, H Maghami, H Mirzaie, M Kareppagoudr, S Dey, ... IEEE Transactions on Circuits and Systems I: Regular Papers 65 (8), 2353-2364, 2018 | 38 | 2018 |
| A Highly Linear OTA-Less 1-1 MASH VCO-Based ADC With an Efficient Phase Quantization Noise Extraction Technique H Maghami, P Payandehnia, H Mirzaie, R Zanbaghi, H Zareie, J Goins, ... IEEE Journal of Solid-State Circuits 55 (3), 706-718, 2019 | 36 | 2019 |
| Fully passive third‐order noise shaping SAR ADC P Payandehnia, H Mirzaie, H Maghami, J Muhlestein, GC Temes Electronics Letters 53 (8), 528-530, 2017 | 29 | 2017 |
| A Highly Linear OTA-Free VCO-Based 1-1 MASH ΔΣ ADC H Maghami, P Payandehnia, H Mirzaie, R Zanbaghi, S Dey, K Mayaram, ... IEEE Transactions on Circuits and Systems I: Regular Papers, 2019 | 28 | 2019 |
| A Highly Linear OTA-Free VCO-Based 1-1 MASH ΔΣ ADC | 28* | 2017 |
| High speed CML latch using active inductor in 0.18 μm CMOS technology P Payandehnia, H Maghami, S Sheikhaei, A Abbasfar, B Forouzandeh, ... 2011 19th Iranian Conference on Electrical Engineering, 1-4, 2011 | 15 | 2011 |
| Passive switched‐capacitor filter with complex poles for high‐speed applications P Payandehnia, H Maghami, M Kareppagoudr, GC Temes Electronics Letters 52 (19), 1592-1594, 2016 | 12 | 2016 |
| A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT Modulator With Inherent DWA H Mirzaie, H Maghami, R Zanbaghi, P Payandehnia, K Mayaram, TS Fiez IEEE Transactions on Circuits and Systems II: Express Briefs 66 (3), 347-351, 2018 | 8 | 2018 |
| High‐linearity SAR‐VCO MASH ΔΣ ADC with second‐order noise shaping P Payandehnia, H Maghami, H Mirzaie, GC Temes Electronics Letters 54 (24), 1366-1368, 2018 | 7 | 2018 |
| 0.9 V, 79.7 dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique H Maghami, P Payandehnia, H Mirzaie, R Zanbaghi, S Dey, J Goins, ... 2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019 | 5 | 2019 |
| A novel time-domain phase quantization noise extraction for a VCO-based quantizer H Maghami, H Mirzaie, P Payandehnia, K Mayaram, R Zanbaghi, T Fiez 2018 IEEE 61st International Midwest Symposium on Circuits and Systems …, 2018 | 5 | 2018 |
| Sequential interstage correlated double sampling: A switched-capacitor technique for high accuracy systems P Payandehnia, H Maghami, X Meng, GC Temes, H Yoshizawa 2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014 | 4 | 2014 |
| A low power 9.5 ENOB 100MS/s pipeline ADC using correlated level shifting K Nanbakhsh, H Maghami, S Sheikhaei, N Masoumi, P Payandehnia 2011 24th Canadian Conference on Electrical and Computer Engineering (CCECE …, 2011 | 3 | 2011 |
| An Amplifier-Free 0–2 SAR-VCO MASH ΔΣ ADC P Payandehnia, H Maghami, H Mirzaie, ML Johnston, GC Temes 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 1 | 2019 |
| High speed CML latch using active inductor in 0.18 CMOS technology PP Nia, H Maghami, S Sheikhaei, A Abbasfar, B Foruzandeh Proc. IEEE Iran. Conf. Elect. Eng.(ICEE), 1-4, 2011 | 1 | 2011 |
| Digital Friendly Continuous-Time Delta-Sigma Analog-to-Digital Converters H Maghami | | 2019 |
| A 0.49-13.3 MHz Tunable 4 th-Order LPF with Complex Poles Achieving 28.7 dBm OIP3 P Payandehnia, H Maghami, H Mirzaie, M Kareppagoudr, S Dey, ... | | |
| Analog and Mixed Mode Circuits and Systems An 85-MHz-BW ASAR-Assisted CT 4-0 MASH∆ Σ Modulator With Background Half-Range Dithering-Based DAC Calibration H Maghami, P Payandehnia, H Mirzaie, R Zanbaghi, S Dey, K Mayaram, ... | | |
Pedram PayandehniaNVIDIA在 ieee.org 的电子邮件经过验证
