| Combinatorial Optimization: Theory and Algorithms B Korte, J Vygen Springer, 2000 | 3939* | 2000 |
| Shorter tours by nicer ears: 7/5-approximation for the graph-TSP, 3/2 for the path version, and 4/3 for two-edge-connected subgraphs A Sebő, J Vygen Combinatorica 34, 597-629, 2014 | 219* | 2014 |
| Algorithms for large-scale flat placement J Vygen Proceedings of the 34th Annual Design Automation Conference, 746-751, 1997 | 168 | 1997 |
| Kombinatorische Optimierung B Korte, J Vygen Springer-Verlag, 2008 | 136* | 2008 |
| A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing S Peyer, D Rautenbach, J Vygen Journal of Discrete Algorithms 7 (4), 377-390, 2009 | 129 | 2009 |
| NP-completeness of some edge-disjoint paths problems J Vygen Discrete Applied Mathematics 61 (1), 83-90, 1995 | 126 | 1995 |
| Approximation Algorithms for Facility Location Problems J Vygen Forschungsinstitut für Diskrete Mathematik, 2005 | 123 | 2005 |
| Bin-packing B Korte, J Vygen Kombinatorische Optimierung, 499-516, 2012 | 122 | 2012 |
| The edge-disjoint paths problem is NP-complete for series–parallel graphs T Nishizeki, J Vygen, X Zhou Discrete Applied Mathematics 115 (1-3), 177-186, 2001 | 97 | 2001 |
| Cycle time and slack optimization for VLSI-chips C Albrecht, B Korte, J Schietke, J Vygen 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of …, 1999 | 89 | 1999 |
| Almost optimum placement legalization by minimum cost flow and dynamic programming U Brenner, A Pauli, J Vygen Proceedings of the 2004 international symposium on Physical design, 2-9, 2004 | 80 | 2004 |
| Clock scheduling and clocktree construction for high performance ASICs S Held, B Korte, J Maßberg, M Ringe, J Vygen ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003 | 75 | 2003 |
| Faster optimal single-row placement with fixed ordering U Brenner, J Vygen Proceedings of the conference on Design, automation and test in Europe, 117-121, 2000 | 75 | 2000 |
| BonnRoute: Algorithms and data structures for fast and good VLSI routing M Gester, D Müller, T Nieberg, C Panten, C Schulte, J Vygen ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (2 …, 2013 | 68* | 2013 |
| Legalizing a placement with minimum total movement U Brenner, J Vygen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 65 | 2004 |
| Algorithms for detailed placement of standard cells J Vygen Proceedings Design, Automation and Test in Europe, 321-324, 1998 | 64 | 1998 |
| BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms U Brenner, M Struzyna, J Vygen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 63 | 2008 |
| On dual minimum cost flow algorithms J Vygen Proceedings of the thirty-second annual ACM symposium on Theory of computing …, 2000 | 56 | 2000 |
| Combinatorial optimization in VLSI design S Held, B Korte, D Rautenbach, J Vygen Combinatorial Optimization: Methods and Applications, 33-96, 2011 | 51 | 2011 |
| An improved approximation algorithm for the asymmetric traveling salesman problem V Traub, J Vygen SIAM Journal on Computing 51 (1), 139-173, 2022 | 48* | 2022 |
Stephan HeldProfessor of Discrete Optimization at University of Bonn在 dm.uni-bonn.de 的电子邮件经过验证
