Agile SoC development with open ESP P Mantovani, D Giri, G Di Guglielmo, L Piccolboni, J Zuckerman, EG Cota, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 115 | 2020 |
Applications and techniques for fast machine learning in science AMC Deiana, N Tran, J Agar, M Blott, G Di Guglielmo, J Duarte, P Harris, ... Frontiers in big Data 5, 787421, 2022 | 56 | 2022 |
ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning D Giri, KL Chiu, G Di Guglielmo, P Mantovani, LP Carloni Design, Automation and Test in Europe Conference (DATE), 2020 | 48 | 2020 |
Accelerators and Coherence: An SoC Perspective D Giri, P Mantovani, LP Carloni IEEE Micro, 2018 | 39 | 2018 |
NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators D Giri, P Mantovani, LP Carloni Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2018 | 36 | 2018 |
Cohmeleon: Learning-based orchestration of accelerator coherence in heterogeneous SoCs J Zuckerman, D Giri, J Kwon, P Mantovani, LP Carloni MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 20 | 2021 |
Accelerator Integration for Open-Source SoC Design D Giri, KL Chiu, G Eichler, P Mantovani, LP Carloni IEEE Micro, 2021 | 20 | 2021 |
A 12nm agile-designed SoC for swarm-based perception with heterogeneous IP blocks, a reconfigurable memory hierarchy, and an 800MHz multi-plane NoC T Jia, P Mantovani, MC Dos Santos, D Giri, J Zuckerman, EJ Loscalzo, ... ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022 | 19 | 2022 |
HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis P Mantovani, R Margelli, D Giri, LP Carloni IEEE Custom Integrated Circuits Conference (CICC), 2020 | 16 | 2020 |
MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems O Matthews, A Manocha, D Giri, M Orenes-Vera, E Tureci, T Sorensen, ... IEEE International Symposium on Performance Analysis of Systems and Software …, 2020 | 15 | 2020 |
A standard cell approach for MagnetoElastic NML circuits D Giri, M Vacca, G Causapruno, W Rao, M Graziano, M Zamboni Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale …, 2014 | 13 | 2014 |
MasterMind: Many-accelerator SoC architecture for real-time brain-computer interfaces G Eichler, L Piccolboni, D Giri, LP Carloni 2021 IEEE 39th International Conference on Computer Design (ICCD), 101-108, 2021 | 11 | 2021 |
Ariane+ NVDLA: Seamless Third-Party IP Integration with ESP D Giri, KL Chiu, G Eichler, P Mantovani, N Chandramoorthy, LP Carloni Workshop on Computer Architecture Research with RISC-V (CARRV), 2020 | 10 | 2020 |
Teaching heterogeneous computing with system-level design methods LP Carloni, EG Cota, GD Guglielmo, D Giri, J Kwon, P Mantovani, ... Proceedings of the Workshop on Computer Architecture Education, 1-8, 2019 | 10 | 2019 |
Modeling, design, and analysis of MagnetoElastic NML circuits D Giri, M Vacca, G Causapruno, M Zamboni, M Graziano IEEE Transactions on Nanotechnology 15 (6), 977-985, 2016 | 10 | 2016 |
Runtime Reconfigurable Memory Hierarchy in Embedded Scalable Platforms D Giri, P Mantovani, LP Carloni Design Automation Conference (ASP-DAC), 2019 24st Asia and South Pacific, 2019 | 9 | 2019 |
DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including … F Gao, TJ Chang, A Li, M Orenes-Vera, D Giri, PJ Jackson, A Ning, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 7 | 2023 |
22.9 A 12nm 18.1 TFLOPs/W sparse transformer processor with entropy-based early exit, mixed-precision predication and fine-grained power management T Tambe, J Zhang, C Hooper, T Jia, PN Whatmough, J Zuckerman, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 342-344, 2023 | 7 | 2023 |
Enabling heterogeneous, multicore soc research with RISC-V and ESP J Zuckerman, P Mantovani, D Giri, LP Carloni arXiv preprint arXiv:2206.01901, 2022 | 7 | 2022 |
Parallel and serial computation in nanomagnet logic: An overview D Giri, G Causapruno, F Riente IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (8 …, 2018 | 6 | 2018 |