| Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 symposium on VLSI technology, T230-T231, 2017 | 848 | 2017 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 182 | 2016 |
| A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 110 | 2014 |
| Channel geometry impact and narrow sheet effect of stacked nanosheet CW Yeung, J Zhang, R Chao, O Kwon, R Vega, G Tsutsui, X Miao, ... 2018 IEEE international electron devices meeting (IEDM), 28.6. 1-28.6. 4, 2018 | 81 | 2018 |
| A novel dry selective etch of SiGe for the enablement of high performance logic stacked gate-all-around nanosheet devices N Loubet, S Kal, C Alix, S Pancharatnam, H Zhou, C Durfee, M Belyansky, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.4. 1-11.4. 4, 2019 | 70 | 2019 |
| Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications J Zhang, J Frougier, A Greene, X Miao, L Yu, R Vega, P Montanini, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2019 | 70 | 2019 |
| High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor J Zhang, T Ando, CW Yeung, M Wang, O Kwon, R Galatage, R Chao, ... 2017 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2017 | 62 | 2017 |
| Methods of forming an isolated nano-sheet transistor device and the resulting device R Xie, SP Adusumilli, K Cheng, P Montanini, R Chao US Patent 9,984,936, 2018 | 45 | 2018 |
| Bottom oxidation through STI (BOTS)—A novel approach to fabricate dielectric isolated FinFETs on bulk substrates K Cheng, S Seo, J Faltermeier, D Lu, T Standaert, I Ok, A Khakifirooz, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 34 | 2014 |
| Towards electrical testable SOI devices using Directed Self-Assembly for fin formation CC Liu, C Estrada-Raygoza, H He, M Cicoria, V Rastogi, N Mohanty, ... Alternative Lithographic Technologies VI 9049, 35-46, 2014 | 30 | 2014 |
| Highly-selective superconformai CVD Ti silicide process enabling area-enhanced contacts for next-generation CMOS architectures N Breil, A Carr, T Kuratomi, C Lavoie, IC Chen, M Stolfi, KD Chiu, W Wang, ... 2017 Symposium on VLSI Technology, T216-T217, 2017 | 25 | 2017 |
| Bias temperature instability reliability in stacked gate-all-around nanosheet transistor M Wang, J Zhang, H Zhou, RG Southwick, RHK Chao, X Miao, VS Basker, ... 2019 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2019 | 22 | 2019 |
| Semiconductor device and method of forming the semiconductor device RH Chao, H Jagannathan, CH Lee, CW Yeung, J Zhang US Patent 10,079,233, 2018 | 22 | 2018 |
| Imaging, modeling and engineering of strain in gate-all-around nanosheet transitors S Reboh, R Coquand, N Loubet, N Bernier, E Augendre, R Chao, J Li, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.5. 1-11.5. 4, 2019 | 19 | 2019 |
| Uniform low-k inner spacer module in gate-all-around (GAA) transistors RH Chao, CH Lee, CW Yeung, J Zhang US Patent 10,243,060, 2019 | 19 | 2019 |
| Electrical test prediction using hybrid metrology and machine learning M Breton, R Chao, GR Muthinti, AA de la Peña, J Simon, AJ Cepler, ... Metrology, Inspection, and Process Control for Microlithography XXXI 10145 …, 2017 | 19 | 2017 |
| Structure and Relative Thermal Stability of Mesoporous (La,Sr)MnO3 Powders Prepared Using Evaporation‐Induced Self‐Assembly Methods R Chao, R Munprom, R Petrova, K Gerdes, JR Kitchin, PA Salvador Journal of the American Ceramic Society 95 (7), 2339-2346, 2012 | 15 | 2012 |
| Advanced in-line metrology strategy for self-aligned quadruple patterning R Chao, M Breton, B L'herron, B Mendoza, R Muthinti, F Nelson, ... Metrology, Inspection, and Process Control for Microlithography XXX 9778 …, 2016 | 14 | 2016 |
| Multitechnique metrology methods for evaluating pitch walking in 14 nm and beyond FinFETs R Chao, KK Kohli, Y Zhang, A Madan, GR Muthinti, AJ Hong, D Conklin, ... Journal of Micro/Nanolithography, MEMS, and MOEMS 13 (4), 041411-041411, 2014 | 14 | 2014 |
| Bottom channel isolation in nanosheet transistors RH Chao, CH Lee, CW Yeung, J Zhang US Patent 10,930,793, 2021 | 13 | 2021 |
