Macromodeling of single-electron transistors for efficient circuit simulation YS Yu, SW Hwang, D Ahn IEEE transactions on electron devices 46 (8), 1667-1671, 1999 | 140 | 1999 |
Fall‐Detection Algorithm Using 3‐Axis Acceleration: Combination with Simple Threshold and Hidden Markov Model D Lim, C Park, NH Kim, SH Kim, YS Yu Journal of Applied Mathematics 2014 (1), 896030, 2014 | 108 | 2014 |
Design challenges and solutions for ultra-high-density monolithic 3D ICs S Panth, S Samal, YS Yu, SK Lim 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S …, 2014 | 53 | 2014 |
Impact of quantum confinement on band-to-band tunneling of line-tunneling type L-shaped tunnel field-effect transistor F Najam, YS Yu IEEE Transactions on Electron Devices 66 (4), 2010-2016, 2019 | 37 | 2019 |
Analytical threshold voltage model including effective conducting path effect (ECPE) for surrounding-gate MOSFETs (SGMOSFETs) with localized charges YS Yu, N Cho, SW Hwang, D Ahn IEEE transactions on electron devices 57 (11), 3176-3180, 2010 | 34 | 2010 |
SPICE macro-modeling for the compact simulation of single electron circuits YS Yu, HS Lee, SW Hwang JOURNAL-KOREAN PHYSICAL SOCIETY 33, S269-S272, 1998 | 34 | 1998 |
One electron-based smallest flexible logic cell SJ Kim, JJ Lee, HJ Kang, JB Choi, YS Yu, Y Takahashi, DG Hasko applied physics letters 101 (18), 2012 | 32 | 2012 |
A unified analytical current model for N-and P-type accumulation-mode (junctionless) surrounding-gate nanowire FETs YS Yu IEEE Transactions on Electron Devices 61 (8), 3007-3010, 2014 | 31 | 2014 |
Single-Electron-Based Flexible Multivalued Exclusive-or Logic Gate SJ Kim, CK Lee, RS Chung, ES Park, SJ Shin, JB Choi, YS Yu, NS Kim, ... IEEE transactions on electron devices 56 (5), 1048-1055, 2009 | 29 | 2009 |
A SPICE-compatible new silicon nanowire field-effect transistors (SNWFETs) model SH Lee, YS Yu, SW Hwang, D Ahn IEEE transactions on nanotechnology 8 (5), 643-649, 2009 | 29 | 2009 |
Transient modelling of single-electron transistors for efficient circuit simulation by SPICE YS Yu, SW Hwang, D Ahn IEE Proceedings-Circuits, Devices and Systems 152 (6), 691-696, 2005 | 29 | 2005 |
Simulation of single-electron/CMOS hybrid circuits using SPICE macro-modeling YS Yu, YI Jung, JH Park, SW Hwang, D Ahn Journal of the Korean Physical Society 35 (SUPPL. 4), S991-S994, 1999 | 29 | 1999 |
Electrical coupling of monolithic 3-D inverters YS Yu, S Panth, SK Lim IEEE Transactions on Electron Devices 63 (8), 3346-3349, 2016 | 28 | 2016 |
Implementation of single electron circuit simulation by SPICE: KOSEC-SPICE YS Yu, JH Oh, SW Hwang 電子情報通信学会技術研究報告= IEICE technical report: 信学技報 100 (147), 85-90, 2000 | 28 | 2000 |
Subthreshold degradation of gate-all-around silicon nanowire field-effect transistors: Effect of interface trap charge BH Hong, N Cho, SJ Lee, YS Yu, L Choi, YC Jung, KH Cho, KH Yeo, ... IEEE electron device letters 32 (9), 1179-1181, 2011 | 24 | 2011 |
Gate-controlled MoTe2 homojunction for sub-thermionic subthreshold swing tunnel field-effect transistor NT Duong, C Park, DH Nguyen, PH Nguyen, TU Tran, DY Park, J Lee, ... Nano Today 40, 101263, 2021 | 23 | 2021 |
Interface trap density of gate-all-around silicon nanowire field-effect transistors with TiN gate: Extraction and compact model F Najam, YS Yu, KH Cho, KH Yeo, DW Kim, JS Hwang, S Kim, SW Hwang IEEE transactions on electron devices 60 (8), 2457-2463, 2013 | 23 | 2013 |
All-analytic surface potential model for SOI MOSFETs YS Yu, SH Kim, SW Hwang, D Ahn IEE Proceedings-Circuits, Devices and Systems 152 (2), 183-188, 2005 | 23 | 2005 |
Equivalent circuit approach for single electron transistor model for efficient circuit simulation by SPICE YS Yu, JH Oh, SW Hwang, D Ahn Electronics Letters 38 (16), 1, 2002 | 19 | 2002 |
Two-dimensional (2D) transition metal dichalcogenide semiconductor field-effect transistors: the interface trap density extraction and compact model F Najam, MLP Tan, R Ismail, YS Yu Semiconductor Science and Technology 30 (7), 075010, 2015 | 17 | 2015 |