Leakage current in sub-micrometer cmos gates PF Butzen, RP Ribas Universidade Federal do Rio Grande do Sul, 1-28, 2006 | 93 | 2006 |
An array-based test circuit for fully automated gate dielectric breakdown characterization J Keane, S Venkatraman, PF Butzen, CH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (5), 787 …, 2011 | 44 | 2011 |
BTI, HCI and TDDB aging impact in flip–flops C Nunes, PF Butzen, AI Reis, RP Ribas Microelectronics Reliability 53 (9-11), 1355-1359, 2013 | 42 | 2013 |
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits PF Butzen, LS da Rosa Jr, EJD Chiappetta Filho, AI Reis, RP Ribas Microelectronics Journal 41 (4), 247-255, 2010 | 38* | 2010 |
Logic synthesis meets machine learning: Trading exactness for generalization S Rai, WL Neto, Y Miyasaka, X Zhang, M Yu, Q Yi, M Fujita, GB Manske, ... 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 35 | 2021 |
Transistor network restructuring against NBTI degradation PF Butzen, V Dal Bem, AI Reis, RP Ribas Microelectronics Reliability 50 (9-11), 1298-1303, 2010 | 25 | 2010 |
Design of CMOS logic gates with enhanced robustness against aging degradation PF Butzen, V Dal Bem, AI Reis, RP Ribas Microelectronics Reliability 52 (9-10), 1822-1826, 2012 | 23 | 2012 |
Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies RB Almeida, CM Marques, PF Butzen, FRG Silva, RAL Reis, C Meinhardt Microelectronics Reliability 88, 196-202, 2018 | 22 | 2018 |
Desenvolvendo o Raciocínio Lógico no Ensino Médio: uma proposta utilizando a ferramenta Scratch FP Mota, NFA Ribeiro, L Emmendorfer, P Butzen, KS Machado, ... Brazilian Symposium on Computers in Education (Simpósio Brasileiro de …, 2014 | 22 | 2014 |
PVT variability analysis of FinFET and CMOS XOR circuits at 16nm FGRG da Silva, PF Butzen, C Meinhardt 2016 IEEE International Conference on Electronics, Circuits and Systems …, 2016 | 15 | 2016 |
Fault masking ratio analysis of majority voters topologies IFV Oliveira, RB Schvittz, PF Butzen 2018 IEEE 19th Latin-American Test Symposium (LATS), 1-6, 2018 | 12 | 2018 |
Impact and optimization of lithography-aware regular layout in digital circuit design V Dal Bem, P Butzen, FS Marranghello, AI Reis, RP Ribas 2011 IEEE 29th International Conference on Computer Design (ICCD), 279-284, 2011 | 11 | 2011 |
Survey on reliability estimation in digital circuits MF Pontes, C Farias, R Schvittz, P Butzen, L da Rosa Jr Journal of Integrated Circuits and Systems 16 (3), 1-11, 2021 | 8 | 2021 |
Single event transient sensitivity analysis of different 32 nm CMOS majority voters designs IFV Oliveira, RB Schvittz, PF Butzen Microelectronics Reliability 100, 113369, 2019 | 8 | 2019 |
Leakage current modeling in Sub-micrometer CMOS complex gates PF Butzen | 8 | 2007 |
Logic synthesis meets machine learning: Trading exactness for generalization. In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) S Rai, WL Neto, Y Miyasaka, X Zhang, M Yu, Q Yi, M Fujita, GB Manske, ... IEEE, 2021 | 7 | 2021 |
Probabilistic method for reliability estimation of sp-networks considering single event transient faults R Schvittz, DT Franco, LS Rosa, PF Butzen 2018 25th IEEE International Conference on Electronics, Circuits and Systems …, 2018 | 7 | 2018 |
The suitability of the spr-mp method to evaluate the reliability of logic circuits MF Pontes, PF Butzen, RB Schvittz, SL Rosa, DT Franco 2018 25th IEEE International Conference on Electronics, Circuits and Systems …, 2018 | 7 | 2018 |
A methodology to evaluate the aging impact on flip-flops performance C Nunes, PF Butzen, AI Reis, RP Ribas 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013 | 7 | 2013 |
BTI and HCI first-order aging estimation for early use in standard cell technology mapping PF Butzen, V Dal Bem, AI Reis, RP Ribas Microelectronics Reliability 53 (9-11), 1360-1364, 2013 | 7 | 2013 |