| Beyond UVM for practical SoC verification YN Yun, JB Kim, ND Kim, B Min 2011 International SoC Design Conference, 158-162, 2011 | 94 | 2011 |
| Sign-off with Bounded Formal Verification Proofs ND Kim, J Park, HG Singh, V Singhal Design and Verification Conference, 2014 | 17 | 2014 |
| How to automate millions lines of top-level uvm testbench and handle huge register classes N Kim, YN Yun, YR Cho, JB Kim, B Min 2012 International SoC Design Conference (ISOCC), 405-407, 2012 | 16 | 2012 |
| Scalable parallel event-driven HDL simulation for multi-cores TB Ahmad, N Kim, B Min, A Kalia, M Ciesielski, S Yang 2012 International Conference on Synthesis, Modeling, Analysis and …, 2012 | 10 | 2012 |
| Millions to thousands issues through knowledge based SoC CDC verification Y Lee, N Kim, JB Kim, B Min 2012 International SoC Design Conference (ISOCC), 391-394, 2012 | 9 | 2012 |
| Predictive parallel event-driven HDL simulation with a new powerful prediction strategy S Yang, J Han, D Kwak, N Kim, D Cha, J Park, J Kim 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-3, 2014 | 5 | 2014 |
| A New Distributed Parallel Event-driven Timing Simulation for ECO Design Changes S Yang, D Kwak, J Han, N Kim SIMUL-2013, Oct, 2013 | 2 | 2013 |
| A fast two-pass hdl simulation with on-demand dump K Shim, Y Cho, N Kim, H Baik, K Kim, D Kim, J Kim, B Min, K Choi, ... 2008 Asia and South Pacific Design Automation Conference, 422-427, 2008 | 2 | 2008 |
| Simulation method based on design checkpoint for efficient debugging KH Shim, ND Kim, IH Park, BE Min, SY Yang The KIPS Transactions: PartA 19 (3), 113-120, 2012 | 1 | 2012 |
| REGO: REconfiGurable system emulatOr ND Kim, SY Yang Journal of the Institute of Electronics Engineers of Korea SD 39 (2), 91-103, 2002 | 1 | 2002 |
| 레고: 재구성 가능한 시스템 에뮬레이터 김남도， 양세양 전자공학회논문지 39 (2), 91-103, 2002 | 1 | 2002 |
| Topology of High Speed System Emulator and Its Software ND Kim, SY Yang The KIPS Transactions: PartA 8 (4), 479-488, 2001 | | 2001 |
