| A charge-based capacitance model for double-gate tunnel FETs with closed-form solution B Lu, H Lu, Y Zhang, Y Zhang, X Cui, Z Lv, S Yang, C Liu IEEE Transactions on Electron Devices 65 (1), 299-307, 2017 | 30 | 2017 |
| Fully analytical carrier-based charge and capacitance model for hetero-gate-dielectric tunneling field-effect transistors B Lu, H Lu, Y Zhang, Y Zhang, X Cui, Z Lv, C Liu IEEE Transactions on Electron Devices 65 (8), 3555-3561, 2018 | 21 | 2018 |
| A novel planar architecture for heterojunction TFETs with improved performance and its digital application as an inverter S Yang, H Lv, B Lu, S Yan, Y Zhang IEEE Access 8, 23559-23567, 2020 | 17 | 2020 |
| A fully analytical current model for tunnel field-effect transistors considering the effects of source depletion and channel charges Z Lyu, H Lu, Y Zhang, Y Zhang, B Lu, X Cui, Y Zhao IEEE Transactions on Electron Devices 65 (11), 4988-4994, 2018 | 16 | 2018 |
| A novel high-performance planar InAs/GaSb face-tunneling FET with implanted drain for leakage current reduction Z Lyu, H Lv, Y Zhang, Y Zhang, Y Zhu, J Sun, M Li, B Lu IEEE Transactions on Electron Devices 68 (3), 1313-1317, 2021 | 15 | 2021 |
| Characteristics of InAs/GaSb line-tunneling FETs with buried drain technique B Lu, Y Cui, A Guo, D Wang, Z Lv, J Zhou, Y Miao IEEE Transactions on Electron Devices 68 (4), 1537-1541, 2021 | 13 | 2021 |
| A Compact Model for Nanowire Tunneling-FETs B Lu, D Wang, Y Cui, Z Li, G Chai, L Dong, J Zhou, G Wang, Y Miao, Z Lv, ... IEEE Transactions on Electron Devices 69 (1), 419-426, 2021 | 10 | 2021 |
| A non-quasi-static model for tunneling FETs based on the relaxation time approximation B Lu, Z Lv, H Lu, Y Cui IEEE Electron Device Letters 40 (12), 1996-1999, 2019 | 8 | 2019 |
| A Fully Analytical Current Model for Gate–Source Overlap Tunneling FETs as the Ternary Devices Z Lyu, H Lu, C Liu, Y Zhang, Y Zhang, Y Zhu, J Sun, B Lu, Z Jia, M Zhao IEEE Transactions on Electron Devices 69 (10), 5900-5905, 2022 | 5 | 2022 |
