| A 90 nm leakage control transistor based clock gating for low power flip flop applications P Bhattacharjee, A Majumder, TD Das 2016 IEEE 59th International Midwest Symposium on Circuits and Systems …, 2016 | 19 | 2016 |
| SPICE Modeling and Analysis for Metal Island Ternary QCA Logic Device P Bhattacharjee, K Das, M De, D De Proceedings of Second International Conference INDIA 2015 1, 33-41, 2015 | 19 | 2015 |
| VLSI Transistor and Interconnect Scaling Overview P Bhattacharjee, A Sadhu Journal of Electronic Design Technology 5 (1), 1-15, 2014 | 12 | 2014 |
| A Variation Aware Robust Gated Flip-Flop for Power Constrained FSM Application P Bhattacharjee, A Majumder Journal of Circuits, Systems, and Computers 28 (07), 1950108, 2019 | 10 | 2019 |
| LECTOR based gated clock approach to design low power FSM for serial adder P Bhattacharjee, A Majumder 2016 IEEE International Symposium on Nanoelectronic and Information Systems …, 2016 | 10 | 2016 |
| Variation aware intuitive clock gating to mitigate on-chip power supply noise A Majumder, P Bhattacharjee International Journal of Electronics 105 (9), 1487-1500, 2018 | 8 | 2018 |
| Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip A Majumder, P Bhattacharjee Nanoelectronic and Information Systems (iNIS), 2017 IEEE International …, 2017 | 8 | 2017 |
| LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications P Bhattacharjee, B Nath, A Majumder International Conference on Electronics, Information, and Communication (ICEIC), 2017 | 7 | 2017 |
| Implementation of 5-Qubit approach-based Shor's Algorithm in IBM Qiskit GR Mounica, G Manimaran, LB Jerome, P Bhattacharjee 2021 IEEE Pune Section International Conference (PuneCon), 1-6, 2021 | 6 | 2021 |
| A 23.52µW / 0.7V Multi-stage Flip-flop Architecture Steered by a LECTOR-based Gated Clock P Bhattacharjee, A Majumder, B Nath IEIE Transactions on Smart Processing and Computing 6 (3), 220-227, 2017 | 6 | 2017 |
| Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges P Bhattacharjee, P Rana, A Majumder "Recent Trends in Communication Networks", ISBN 978-1-83880-507-4, 2019 | 5 | 2019 |
| A variation tolerant data dependent clock gating approach for PSN attenuated low power digital IC P Bhattacharjee, D Sarkar, A Majumder Ain Shams Engineering Journal 10 (3), 573-585, 2019 | 3 | 2019 |
| A novel gating approach to alleviate power and ground noise in silicon chips A Majumder, P Bhattacharjee, TD Das Journal of Circuits, Systems and Computers 27 (09), 1850146, 2018 | 3 | 2018 |
| Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell P Bhattacharjee, K Das, A Dey, D De, SK Chakraborty Journal of Low Power Electronics 13 (2), 231-239, 2017 | 3 | 2017 |
| Performance Estimation of VLSI Design A Sadhu, P Bhattacherjee, S Koley Journal of VLSI Design Tools & Technology 4 (2), 59-66, 2014 | 3 | 2014 |
| Methodology of Standard Cell Library Design in. LIB Format A Sadhu, P Bhattacharjee Journal of VLSI Design Tools & Technology 4 (1), 30-38, 2014 | 3 | 2014 |
| Clock-gated variable frequency signaling to alleviate power supply noise in a packaged IC P Bhattacharjee, P Rana, BK Bhattacharyya, A Majumder IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 2 | 2021 |
| A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time P Bhattacharjee, BK Bhattacharyya, A Majumder Circuits, Systems, and Signal Processing 40 (4), 1569-1588, 2020 | 2 | 2020 |
| Data-Dependent Clock Gating approach for Low Power Sequential System D Sarkar, P Bhattacharjee, A Majumder MICRO-2018, Bhubaneswar, India (5th International Conference on …, 2018 | 2 | 2018 |
| SPICE modeling for metal island charged confined cellular automata P Bhattacharjee, K Das Journal of Computational and Theoretical Nanoscience 14 (5), 2326-2331, 2017 | 2 | 2017 |
Alak MajumderAssistant Professor, NIT Arunachal Pradesh, India在 nitap.ac.in 的电子邮件经过验证
