| Double node upsets hardened latch circuits Y Li, H Wang, S Yao, X Yan, Z Gao, J Xu Journal of Electronic Testing 31, 537-548, 2015 | 80 | 2015 |
| Single event transient and TID study in 28 nm UTBB FDSOI technology R Liu, A Evans, L Chen, Y Li, M Glorieux, R Wong, SJ Wen, J Cunha, ... IEEE Transactions on Nuclear Science 64 (1), 113-118, 2016 | 58 | 2016 |
| A quatro-based 65-nm flip-flop circuit for soft-error resilience YQ Li, HB Wang, R Liu, L Chen, I Nofal, ST Shi, AL He, G Guo, SH Baeg, ... IEEE Transactions on Nuclear Science 64 (6), 1554-1561, 2017 | 52 | 2017 |
| An SEU-tolerant DICE latch design with feedback transistors HB Wang, YQ Li, L Chen, LX Li, R Liu, S Baeg, N Mahatme, BL Bhuva, ... IEEE Transactions on Nuclear Science 62 (2), 548-554, 2015 | 48 | 2015 |
| Supply voltage dependence of heavy ion induced SEEs on 65 nm CMOS bulk SRAMs Q Wu, Y Li, L Chen, A He, G Guo, SH Baeg, H Wang, R Liu, L Li, SJ Wen, ... IEEE Transactions on Nuclear Science 62 (4), 1898-1904, 2015 | 38 | 2015 |
| Evaluation of SEU performance of 28-nm FDSOI flip-flop designs HB Wang, JS Kauppila, K Lilja, M Bounasser, L Chen, M Newton, YQ Li, ... IEEE Transactions on Nuclear Science 64 (1), 367-373, 2016 | 33 | 2016 |
| An area efficient SEU-tolerant latch design HB Wang, JS Bi, ML Li, L Chen, R Liu, YQ Li, AL He, G Guo IEEE Transactions on Nuclear Science 61 (6), 3660-3666, 2014 | 29 | 2014 |
| An area efficient stacked latch design tolerant to SEU in 28 nm FDSOI technology HB Wang, L Chen, R Liu, YQ Li, JS Kauppila, BL Bhuva, K Lilja, SJ Wen, ... IEEE Transactions on Nuclear Science 63 (6), 3003-3009, 2016 | 27 | 2016 |
| Design of SRAM-based low-cost SEU monitor for self-adaptive multiprocessing systems J Chen, M Andjelkovic, A Simevski, Y Li, P Skoncej, M Krstic 2019 22nd Euromicro conference on digital system design (DSD), 514-521, 2019 | 26 | 2019 |
| A 65 nm temporally hardened flip-flop circuit YQ Li, HB Wang, R Liu, L Chen, I Nofal, QY Chen, AL He, G Guo, ... IEEE Transactions on Nuclear Science 63 (6), 2934-2940, 2016 | 24 | 2016 |
| Single-event transient sensitivity evaluation of clock networks at 28-nm CMOS technology HB Wang, N Mahatme, L Chen, M Newton, YQ Li, R Liu, M Chen, ... IEEE Transactions on Nuclear Science 63 (1), 385-391, 2016 | 24 | 2016 |
| Use of decoupling cells for mitigation of SET effects in CMOS combinational gates M Andjelkovic, M Babic, Y Li, O Schrape, M Krstic, R Kraemer 2018 25th IEEE International Conference on Electronics, Circuits and Systems …, 2018 | 16 | 2018 |
| Analysis of advanced circuits for SET measurement R Liu, A Evans, Q Wu, Y Li, L Chen, SJ Wen, R Wong, R Fung 2015 IEEE International Reliability Physics Symposium, SE. 7.1-SE. 7.7, 2015 | 13 | 2015 |
| A self-checking approach for SEU/MBUs-hardened FSMs design based on the replication of one-hot code L Yuanqing, Y Suying, X Jiangtao, G Jing IEEE Transactions on Nuclear Science 59 (5), 2572-2579, 2012 | 11 | 2012 |
| A novel built-in current sensor for N-WELL SET detection HB Wang, R Liu, L Chen, JS Bi, ML Li, YQ Li Journal of Electronic Testing 31, 395-401, 2015 | 9 | 2015 |
| A 10-transistor 65 nm SRAM cell tolerant to single-event upsets Y Li, L Li, Y Ma, L Chen, R Liu, H Wang, Q Wu, M Newton, M Chen Journal of Electronic Testing 32, 137-145, 2016 | 8 | 2016 |
| Double cell upsets mitigation through triple modular redundancy Y Li, A Breitenreiter, M Andjelkovic, J Chen, M Babic, M Krstic Microelectronics Journal 96, 104683, 2020 | 7 | 2020 |
| Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree Y Li, L Chen, I Nofal, M Chen, H Wang, R Liu, Q Chen, M Krstic, S Shi, ... Microelectronics Reliability 87, 24-32, 2018 | 6 | 2018 |
| Simulation and experimental evaluation of a soft error tolerant layout for SRAM 6T bitcell in 65nm technology L Li, Y Li, H Wang, R Liu, Q Wu, M Newton, Y Ma, L Chen Journal of Electronic Testing 31, 561-568, 2015 | 5 | 2015 |
| Characterization and modeling of SET generation effects in CMOS Standard logic cells M Andjelkovic, Y Li, Z Stamenkovic, M Krstic, R Kraemer 2019 IEEE 25th International Symposium on On-Line Testing and Robust System …, 2019 | 4 | 2019 |
