Temperature-aware microarchitecture K Skadron, MR Stan, W Huang, S Velusamy, K Sankaranarayanan, ... ACM SIGARCH Computer Architecture News 31 (2), 2-13, 2003 | 1664 | 2003 |
Bus-invert coding for low-power I/O MR Stan, WP Burleson IEEE Transactions on very large scale integration (VLSI) systems 3 (1), 49-58, 1995 | 1457 | 1995 |
HotSpot: A compact thermal modeling methodology for early-stage VLSI design W Huang, S Ghosh, S Velusamy, K Sankaranarayanan, K Skadron, ... IEEE Transactions on very large scale integration (VLSI) systems 14 (5), 501-513, 2006 | 1288 | 2006 |
Temperature-aware microarchitecture: Modeling and implementation K Skadron, MR Stan, K Sankaranarayanan, W Huang, S Velusamy, ... ACM Transactions on Architecture and Code Optimization (TACO) 1 (1), 94-125, 2004 | 958 | 2004 |
Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management K Skadron, T Abdelzaher, MR Stan Proceedings Eighth International Symposium on High Performance Computer …, 2002 | 560 | 2002 |
Relaxing non-volatility for fast and energy-efficient STT-RAM caches CW Smullen, V Mohan, A Nigam, S Gurumurthi, MR Stan 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 530 | 2011 |
Advances and future prospects of spin-transfer torque random access memory E Chen, D Apalkov, Z Diao, A Driskill-Smith, D Druist, D Lottis, V Nikitin, ... IEEE Transactions on Magnetics 46 (6), 1873-1878, 2010 | 513 | 2010 |
Compact thermal modeling for temperature-aware design W Huang, MR Stan, K Skadron, K Sankaranarayanan, S Ghosh, ... Proceedings of the 41st annual design automation conference, 878-883, 2004 | 460 | 2004 |
The promise of nanomagnetics and spintronics for future logic and universal memory SA Wolf, J Lu, MR Stan, E Chen, DM Treger Proceedings of the IEEE 98 (12), 2155-2168, 2010 | 409 | 2010 |
Molecular electronics: From devices and interconnect to circuits and architecture MR Stan, PD Franzon, SC Goldstein, JC Lach, MM Ziegler Proceedings of the IEEE 91 (11), 1940-1957, 2003 | 373 | 2003 |
Hotleakage: A temperature-aware model of subthreshold and gate leakage for architects Y Zhang, D Parikh, K Sankaranarayanan, K Skadron, M Stan Technical Report CS-2003-05, University of Virginia, 2003 | 372 | 2003 |
A case for thermal-aware floorplanning at the microarchitectural level K Sankaranarayanan, S Velusamy, M Stan, K Skadron Journal of Instruction-Level Parallelism 7 (1), 8-16, 2005 | 263 | 2005 |
CMOS/nano co-design for crossbar-based molecular electronic systems MM Ziegler, MR Stan IEEE Transactions on Nanotechnology 2 (4), 217-230, 2003 | 247 | 2003 |
Low-power encodings for global communication in CMOS VLSI MR Stan, WP Burleson IEEE transactions on very large scale integration (VLSI) systems 5 (4), 444-455, 1997 | 235 | 1997 |
Circuit-level techniques to control gate leakage for sub-100nm CMOS F Hamzaoglu, MR Stan Proceedings of the 2002 international symposium on Low power electronics and …, 2002 | 189 | 2002 |
Odd/even bus invert with two-phase transfer for buses with coupling Y Zhang, J Lach, K Skadron, MR Stan Proceedings of the 2002 international symposium on Low power electronics and …, 2002 | 179 | 2002 |
Power issues related to branch prediction D Parikh, K Skadron, Y Zhang, M Barcella, MR Stan Proceedings Eighth International Symposium on High Performance Computer …, 2002 | 169 | 2002 |
Scaling with design constraints: Predicting the future of big chips W Huang, K Rajamani, MR Stan, K Skadron IEEE Micro 31 (4), 16-29, 2011 | 167 | 2011 |
Perfect 3-limited-weight code for low power I/O MR Stan, Y Zhang International Workshop on Power and Timing Modeling, Optimization and …, 2004 | 163 | 2004 |
Temperature-aware computer systems: Opportunities and challenges K Skadron, MR Stan, W Huang, S Velusamy, K Sankaranarayanan, ... IEEE Micro 23 (6), 52-61, 2003 | 159 | 2003 |