| On-chip TSV testing for 3D IC before bonding using sense amplification PY Chen, CW Wu, DM Kwai 2009 Asian Test Symposium, 450-455, 2009 | 177 | 2009 |
| On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding PY Chen, CW Wu, DM Kwai 2010 28th VLSI Test Symposium (VTS), 263-268, 2010 | 152 | 2010 |
| A unified formulation of honeycomb and diamond networks B Parhami, DM Kwai IEEE Transactions on Parallel and Distributed Systems 12 (1), 74-80, 2001 | 92 | 2001 |
| A built-in self-test scheme for the post-bond test of TSVs in 3D ICs YJ Huang, JF Li, JJ Chen, DM Kwai, YF Chou, CW Wu 29th VLSI test symposium, 20-25, 2011 | 90 | 2011 |
| Performance characterization of TSV in 3D IC via sensitivity analysis JW You, SY Huang, DM Kwai, YF Chou, CW Wu 2010 19th IEEE Asian Test Symposium, 389-394, 2010 | 79 | 2010 |
| Small delay testing for TSVs in 3-D ICs SY Huang, YH Lin, KH Tsai, WT Cheng, S Sunter, YF Chou, DM Kwai Proceedings of the 49th Annual Design Automation Conference, 1031-1036, 2012 | 73 | 2012 |
| Image capture device CW Wu, DM Kwai, J Li, KY Yeh US Patent App. 12/977,495, 2012 | 69 | 2012 |
| Method for testing through-silicon-via and the circuit thereof CW Wu, PY Chen, DM Kwai, YF Chou US Patent 8,531,199, 2013 | 46 | 2013 |
| Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization CL Lung, YL Ho, DM Kwai, SC Chang 2011 Design, Automation & Test in Europe, 1-6, 2011 | 44 | 2011 |
| Parametric delay test of post-bond through-silicon vias in 3-D ICs via variable output thresholding analysis YH Lin, SY Huang, KH Tsai, WT Cheng, S Sunter, YF Chou, DM Kwai IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 42 | 2013 |
| Practical considerations in applying/spl Sigma/-/spl Delta/modulation-based analog BIST to sampled-data systems HC Hong, JL Huang, KT Cheng, CW Wu, DM Kwai IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2003 | 42 | 2003 |
| In-situ method for TSV delay testing and characterization using input sensitivity analysis JW You, SY Huang, YH Lin, MH Tsai, DM Kwai, YF Chou, CW Wu IEEE transactions on very large scale integration (VLSI) systems 21 (3), 443-453, 2012 | 39 | 2012 |
| Detection of SRAM cell stability by lowering array supply voltage DM Kwai, HW Chang, HJ Liao, CH Chiao, YF Chou Proceedings of the Ninth Asian Test Symposium, 268-273, 2000 | 39 | 2000 |
| A test integration methodology for 3D integrated circuits CW Chou, JF Li, JJ Chen, DM Kwai, YF Chou, CW Wu 2010 19th IEEE Asian Test Symposium, 377-382, 2010 | 37 | 2010 |
| Method for testing through-silicon-via and the circuit thereof CW WU, PY Chen, DM Kwai, YF Chou US Patent App. 12/572,030, 2011 | 34 | 2011 |
| Periodically regular chordal rings B Parhami, DM Kwai IEEE Transactions on parallel and Distributed Systems 10 (6), 658-672, 1999 | 34 | 1999 |
| Stacked structure and stacked method for three-dimensional chip YF Chou, DM Kwai US Patent 8,710,676, 2014 | 33 | 2014 |
| Data-driven control scheme for linear arrays: application to a stable insertion sorter B Parhami, DM Kwai IEEE Transactions on Parallel and Distributed Systems 10 (1), 23-28, 1999 | 33 | 1999 |
| Electrostatic discharge protection scheme for semiconductor device stacking process ZW Jiang, DM Kwai, SH Chen US Patent App. 12/851,539, 2011 | 26 | 2011 |
| Yield enhancement by bad-die recycling and stacking with though-silicon vias YF Chou, DM Kwai, CW Wu IEEE transactions on very large scale integration (VLSI) systems 19 (8 …, 2010 | 26 | 2010 |
Cheng-Wen Wu 吳誠文Department of Electrical Engineering, National Tsing Hua University在 ee.nthu.edu.tw 的电子邮件经过验证
