| Low-power single-and double-edge-triggered flip-flops for high-speed applications SH Rasouli, A Khademzadeh, A Afzali-Kusha, M Nourani IEE Proceedings-Circuits, Devices and Systems 152 (2), 118-122, 2005 | 111 | 2005 |
| Design optimization of FinFET domino logic considering the width quantization property SH Rasouli, HF Dadgour, K Endo, H Koike, K Banerjee IEEE transactions on electron devices 57 (11), 2934-2943, 2010 | 48 | 2010 |
| Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization SH Rasouli, K Endo, K Banerjee Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 26 | 2009 |
| Grain-orientation induced quantum confinement variation in FinFETs and multi-gate ultra-thin body CMOS devices and implications for digital design SH Rasouli, K Endo, JF Chen, N Singh, K Banerjee IEEE transactions on electron devices 58 (8), 2282-2292, 2011 | 20 | 2011 |
| Layout construction for addressing electromigration SH Rasouli, MJ Brunolli, CSA Hau-Riege, M Malabry, SK Harish, ... US Patent 9,972,624, 2018 | 16 | 2018 |
| Double edge triggered feedback flip-flop in sub 100nm technology SH Rasouli, A Amirabadi, A Seyedi, A Afzali-Kusha Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 16 | 2006 |
| High performance standard cell with continuous oxide definition and characterized leakage current X Chen, O Kwon, F Vang, A Datta, SH Rasouli US Patent 9,318,476, 2016 | 13 | 2016 |
| High-speed low-power FinFET based domino logic SH Rasouli, H Koike, K Banerjee 2009 Asia and South Pacific Design Automation Conference, 829-834, 2009 | 13 | 2009 |
| Clock-gating cell with low area, low power, and low setup time SH Rasouli, SJ Dillen, A Datta US Patent 9,577,635, 2017 | 12 | 2017 |
| A physical model for work-function variation in ultra-short channel metal-gate MOSFETs SH Rasouli, C Xu, N Singh, K Banerjee IEEE electron device letters 32 (11), 1507-1509, 2011 | 11 | 2011 |
| Flip-flop with reduced retention voltage SH Rasouli, A Datta, JM Shah, M Saint-Laurent, PK Parkar, S Bapat, ... US Patent 9,673,786, 2017 | 7 | 2017 |
| High frequency synchronizer SH Rasouli, A Datta, S Marimuthu, O Kwon US Patent 9,020,084, 2015 | 7 | 2015 |
| Clock-gated synchronizer SH Rasouli, A Datta, O Kwon US Patent App. 13/767,729, 2014 | 7 | 2014 |
| Low power and high performance clock delayed domino logic using saturated keeper A Amirabadi, A Chehelcheraghi, SH Rasouli, A Seyedi, A Afzai-Kusha 2006 IEEE International Symposium on Circuits and Systems, 4 pp.-3176, 2006 | 7 | 2006 |
| Clock gated static pulsed flip-flop (CGSPFF) in sub 100 nm technology AS Seyedi, SH Rasouli, A Amirabadi, A Afzali-Kusha IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and …, 2006 | 7 | 2006 |
| Layout construction for addressing electromigration SH Rasouli, A Datta, O Kwon US Patent 10,580,774, 2020 | 6 | 2020 |
| Layout construction for addressing electromigration SH Rasouli, A Datta, O Kwon US Patent 10,074,609, 2018 | 6 | 2018 |
| Semi-data gated flop with low clock power/low internal power with minimal area overhead SH Rasouli, X Chen, V Boynapalli US Patent 9,979,381, 2018 | 6 | 2018 |
| Low power low leakage clock gated static pulsed flip-flop AS Seyedi, SH Rasouli, A Amirabadi, A Afzali-Kusha 2006 IEEE International Symposium on Circuits and Systems, 4 pp.-3661, 2006 | 6 | 2006 |
| Race-free CMOS pass-gate charge recycling logic (FCPCL) for low power applications A Abbasian, SH Rasouli, J Derakhshandeh, A Afzali-Kusha, M Nourani Southwest Symposium on Mixed-Signal Design, 2003., 87-89, 2003 | 6 | 2003 |
