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Anand Raj
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Vertically Extended Drain Double Gate Si1−xGex Source Tunnel FET : Proposal & Investigation For Optimized Device Performance
A Raj, S Singh, KN Priyadarshani, R Arya, A Naugarhiya
Silicon 13, 2589-2604, 2021
222021
Impact of temperature and interface trapped charges variation on the Analog/RF and linearity of vertically extended drain double gate Si0. 5Ge0. 5 source tunnel FET
P Kumari, A Raj, KN Priyadarshani, S Singh
Microelectronics Journal 113, 105077, 2021
172021
DeepAttack: A deep learning based oracle-less attack on logic locking
A Raj, N Avula, P Das, D Sisejkovic, F Merchant, A Acharyya
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023
32023
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