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Ritu Singal
Ritu Singal
Component Design Engineer
在 intel.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
Design rule optimization of regular layout for leakage reduction in nanoscale design
AR Subramaniam, R Singhal, CC Wang, Y Cao
2008 Asia and South Pacific Design Automation Conference, 474-479, 2008
1232008
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation
R Singhal, A Balijepalli, A Subramaniam, F Liu, S Nassif, Y Cao
Proceedings of the 44th annual Design Automation Conference, 823-828, 2007
772007
Leakage reduction through optimization of regular layout parameters
AR Subramaniam, R Singhal, CC Wang, Y Cao
Microelectronics Journal 43 (1), 25-33, 2012
42012
Modeling and analysis of the nonrectangular gate effect for postlithography circuit simulation
R Singal, A Balijepalli, A Subramaniam, CC Wang, F Liu, SR Nassif, ...
IEEE transactions on very large scale integration (VLSI) systems 18 (4), 666-670, 2009
12009
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