| Automatic discovery of RTL benchmark circuits with predefined testability properties T Pecenka, Z Kotásek, L Sekanina, J Strnadel 2005 NASA/DoD Conference on Evolvable Hardware (EH'05), 51-58, 2005 | 28 | 2005 |
| Testability analysis and improvements of register-transfer level digital circuits J Strnadel Computing and Informatics 25 (5), 441-464, 2006 | 24 | 2006 |
| Testability improvements based on the combination of analytical and evolutionary approaches at RT level J Strnadel, Z Kotásek Proceedings Euromicro Symposium on Digital System Design. Architectures …, 2002 | 15 | 2002 |
| Interactive tool for behavioral level testability analysis J Hlavička, Z Kotásek, R Růžička, J Strnadel Proceedings of the IEEE ETW, 117-119, 2001 | 15 | 2001 |
| Monitoring-Driven HW/SW Interrupt Overload Prevention for Embedded Real-Time Systems J Strnadel 15th International IEEE Symposium on Design and Diagnostics of Electronic …, 2012 | 14* | 2012 |
| Reduction of power dissipation through parallel optimization of test vector and scan register sequences Z Kotasek, J Skarvada, J Strnadel 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and …, 2010 | 12 | 2010 |
| Normalized testability measures based on rtl digital circuit graph model analysis J Strnadel Proceedings of 5th International Scientific Conference Electronic Computers …, 2002 | 12 | 2002 |
| Formal and analytical approaches to the testability analysis-The comparison Z Kotásek, R Růžička, J Strnadel Proceedings of IEEE Design and Diagnostics of Electronic Circuits and …, 2001 | 12 | 2001 |
| Evolutionary design of synthetic RTL benchmark circuits Z Kotásek, T Pečenka, L Sekanina, J Strnadel IEEE European Test Workshop, 107-108, 2004 | 10 | 2004 |
| Testability estimation based on controllability and observability parameters T Pecenka, J Strnadel, Z Kotásek, L Sekanina 9th EUROMICRO Conference on Digital System Design (DSD'06), 504-514, 2006 | 9 | 2006 |
| Test scheduling for embedded systems Z Kotásek, D Mika, J Strnadel Euromicro Symposium on Digital System Design, 2003. Proceedings., 463-467, 2003 | 8 | 2003 |
| Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates J Strnadel Architecture of Computing Systems - ARCS 2013 7767, 98-109, 2013 | 7 | 2013 |
| Improving testability parameters of pipelined circuits through the identification of testable cores Z Kotásek, T Pečenka, J Strnadel Proc. of the 7th IEEE Workshop on Design and Diagnostics of Electronic …, 2004 | 7 | 2004 |
| Methodologies of RTL partial scan analysis and their comparison Z Kotásek, D Mika, J Strnadel Proceedings of IEEE Workshop on Design and Diagnostic of Electronic Circuits …, 2003 | 7 | 2003 |
| Two Level Testability System Z Kotásek, R Růžička, J Strnadel, F Zbořil Proceedings of the 35th Spring International Conference MOSIS 1, 433-440, 2001 | 7 | 2001 |
| Scan layout encoding by means of a binary string J Strnadel Proceedings of of 37th International Conference on Modelling and Simulation …, 2003 | 6 | 2003 |
| Optimising Solution of the Scan Problem at RT Level Based on a Genetic Algorithm J Strnadel, Z Kotásek Proc. of 5th IEEE Design and Diagnostics of Electronics Circuits and Systems …, 2002 | 6 | 2002 |
| On creation and analysis of reliability models by means of stochastic timed automata and statistical model checking: Principle J Strnadel International Symposium on Leveraging Applications of Formal Methods, 166-181, 2016 | 5 | 2016 |
| The use of genetic algorithm to derive correlation between test vector and scan register sequences and reduce power consumption Z Kotásek, J Škarvada, J Strnadel 2010 13th Euromicro Conference on Digital System Design: Architectures …, 2010 | 5 | 2010 |
| Návrh časově kritických systémů I: specifikace a verifikace J Strnadel Automa 2010 (10), 42-44, 2010 | 5 | 2010 |
Lukas SekaninaProfessor of Computer Science and Engineering, Brno University of Technology在 fit.vutbr.cz 的电子邮件经过验证
