| Matrix multiplication on heterogeneous platforms O Beaumont, V Boudet, F Rastello, Y Robert IEEE Transactions on Parallel and Distributed Systems 12 (10), 1033-1051, 2001 | 241 | 2001 |
| A proposal for a heterogeneous cluster ScaLAPACK (dense linear solvers) O Beaumont, V Boudet, A Petitet, F Rastello, Y Robert IEEE Transactions on Computers 50 (10), 1052-1070, 2001 | 130 | 2001 |
| A framework for enhancing data reuse via associative reordering K Stock, M Kong, T Grosser, LN Pouchet, F Rastello, J Ramanujam, ... Proceedings of the 35th ACM SIGPLAN Conference on Programming Language …, 2014 | 85 | 2014 |
| Register allocation: What does the NP-completeness proof of Chaitin et al. really prove? or revisiting register allocation: Why and how F Bouchez, A Darte, C Guillon, F Rastello International Workshop on Languages and Compilers for Parallel Computing …, 2006 | 85 | 2006 |
| Partitioning a square into rectangles: NP-completeness and approximation algorithms Beaumont, Boudet, Rastello Algorithmica 34, 217-239, 2002 | 77 | 2002 |
| Revisiting out-of-SSA translation for correctness, code quality and efficiency B Boissinot, A Darte, F Rastello, BD de Dinechin, C Guillon 2009 International Symposium on Code Generation and Optimization, 114-125, 2009 | 70 | 2009 |
| Algorithmic issues on heterogeneous computing platforms P Boulet, J Dongarra, F Rastello, Y Robert, F Vivien Parallel processing letters 9 (02), 197-213, 1999 | 66 | 1999 |
| Register optimizations for stencils on GPUs PS Rawat, F Rastello, A Sukumaran-Rajam, LN Pouchet, A Rountev, ... Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of …, 2018 | 63 | 2018 |
| On the complexity of register coalescing F Bouchez, A Darte, F Rastello International symposium on code generation and optimization (CGO'07), 102-114, 2007 | 59 | 2007 |
| Static and dynamic frequency scaling on multicore CPUs W Bao, C Hong, S Chunduri, S Krishnamoorthy, LN Pouchet, F Rastello, ... ACM Transactions on Architecture and Code Optimization (TACO) 13 (4), 1-26, 2016 | 58 | 2016 |
| Determining the idle time of a tiling: New results F Desprez, J Dongarra, F Rastello, Y Robert Proceedings 1997 International Conference on Parallel Architectures and …, 1997 | 44 | 1997 |
| Runtime pointer disambiguation P Alves, F Gruber, J Doerfert, A Lamprineas, T Grosser, F Rastello, ... Proceedings of the 2015 ACM SIGPLAN International Conference on Object …, 2015 | 39 | 2015 |
| Procedure placement using temporal-ordering information: dealing with code size expansion C Guillon, F Rastello, T Bidault, F Bouchez Proceedings of the 2004 international conference on Compilers, architecture …, 2004 | 38 | 2004 |
| Effective padding of multidimensional arrays to avoid cache conflict misses C Hong, W Bao, A Cohen, S Krishnamoorthy, LN Pouchet, F Rastello, ... ACM SIGPLAN Notices 51 (6), 129-144, 2016 | 37 | 2016 |
| Polycheck: Dynamic verification of iteration space transformations on affine programs W Bao, S Krishnamoorthy, LN Pouchet, F Rastello, P Sadayappan ACM SIGPLAN Notices 51 (1), 539-554, 2016 | 37 | 2016 |
| Register allocation and spill complexity under SSA F Bouchez, A Darte, C Guillon, F Rastello Laboratoire de l'informatique du parallélisme, 2005 | 36 | 2005 |
| Using data dependencies to improve task-based scheduling strategies on NUMA architectures P Virouleau, F Broquedis, T Gautier, F Rastello Euro-Par 2016: Parallel Processing: 22nd International Conference on …, 2016 | 35 | 2016 |
| Optimizing translation out of SSA using renaming constraints F Rastello, F de Ferriere, C Guillon International Symposium on Code Generation and Optimization, 2004. CGO 2004 …, 2004 | 35 | 2004 |
| SSA-based Compiler Design F Rastello, FB Tichadou Springer, 2022 | 34 | 2022 |
| On the complexity of spill everywhere under SSA form F Bouchez, A Darte, F Rastello ACM SIGPLAN Notices 42 (7), 103-112, 2007 | 34 | 2007 |
Louis-Noel PouchetColorado State University在 colostate.edu 的电子邮件经过验证
