| Design of a novel reversible multiplier circuit using HNG gate in nanotechnology M Haghparast, SJ Jassbi, K Navi, O Hashemipour World Applied Sciences Journal 3 (6), 974-978, 2008 | 242 | 2008 |
| Two new low-power full adders based on majority-not gates K Navi, MH Moaiyeri, RF Mirzaee, O Hashemipour, BM Nezhad Microelectronics journal 40 (1), 126-130, 2009 | 186 | 2009 |
| A universal method for designing low‐power carbon nanotube FET‐based multiple‐valued logic circuits MH Moaiyeri, RF Mirzaee, A Doostaregan, K Navi, O Hashemipour IET Computers & Digital Techniques 7 (4), 167-181, 2013 | 137 | 2013 |
| Efficient CNTFET-based ternary full adder cells for nanoelectronics MH Moaiyeri, RF Mirzaee, K Navi, O Hashemipour Nano-Micro Letters 3, 43-50, 2011 | 99 | 2011 |
| Design and evaluation of CNFET-based quaternary circuits MH Moaiyeri, K Navi, O Hashemipour Circuits, Systems, and Signal Processing 31, 1631-1652, 2012 | 87 | 2012 |
| High speed capacitor-inverter based carbon nanotube full adder K Navi, M Rashtian, A Khatir, P Keshavarzian, O Hashemipour Nanoscale research letters 5, 859-862, 2010 | 78 | 2010 |
| Enhancing transconductance of ultra‐low‐power two‐stage folded cascode OTA M Akbari, O Hashemipour Electronics Letters 50 (21), 1514-1516, 2014 | 54 | 2014 |
| DCCII based frequency compensation method for three stage amplifiers S Shahsavari, S Biabanifard, SMH Largani, O Hashemipour AEU-International Journal of Electronics and Communications 69 (1), 176-181, 2015 | 53 | 2015 |
| A 0.6-V, 0.4-µW bulk-driven operational amplifier with rail-to-rail input/output swing M Akbari, O Hashemipour Analog Integrated Circuits and Signal Processing 86, 341-351, 2016 | 46 | 2016 |
| Design and analysis of folded cascode OTAs using Gm/Id methodology based on flicker noise reduction M Akbari, O Hashemipour Analog Integrated Circuits and Signal Processing 83, 343-352, 2015 | 44 | 2015 |
| A high-speed current conveyor based current comparator R Chavoshisani, O Hashemipour Microelectronics Journal 42 (1), 28-32, 2011 | 40 | 2011 |
| High-performance mixed-mode universal min-max circuits for nanotechnology MH Moaiyeri, R Chavoshisani, A Jalali, K Navi, O Hashemipour Circuits, Systems, and Signal Processing 31, 465-488, 2012 | 38 | 2012 |
| Dramatically low-transistor-count high-speed ternary adders RF Mirzaee, MH Moaiyeri, M Maleknejad, K Navi, O Hashemipour 2013 IEEE 43rd International Symposium on Multiple-Valued Logic, 170-175, 2013 | 37 | 2013 |
| Improving power efficiency of a two-stage operational amplifier for biomedical applications M Akbari, M Nazari, L Sharifi, O Hashemipour Analog Integrated Circuits and Signal Processing 84, 173-183, 2015 | 35 | 2015 |
| Differential cascode voltage switch (DCVS) strategies by CNTFET technology for standard ternary logic RF Mirzaee, T Nikoubin, K Navi, O Hashemipour Microelectronics Journal 44 (12), 1238-1250, 2013 | 35 | 2013 |
| An efficient architecture for designing reverse converters based on a general three-moduli set AS Molahosseini, K Navi, O Hashemipour, A Jalali journal of Systems Architecture 54 (10), 929-934, 2008 | 35 | 2008 |
| A 63‐dB gain OTA operating in subthreshold with 20‐nW power consumption M Akbari, O Hashemipour International Journal of Circuit Theory and Applications 45 (6), 843-850, 2017 | 34 | 2017 |
| A high input dynamic range, low voltage cascode current mirror and enhanced phase-margin folded cascode amplifier M Akbari, A Javid, O Hashemipour 2014 22nd Iranian Conference on Electrical Engineering (ICEE), 77-81, 2014 | 31 | 2014 |
| Design of ultra-low-power CMOS amplifiers based on flicker noise reduction M Akbari, S Biabanifard, O Hashemipour 2014 22nd Iranian conference on electrical engineering (ICEE), 403-406, 2014 | 31 | 2014 |
| Systematic design of analog integrated circuits using ant colony algorithm based on noise optimization M Akbari, M Shokouhifar, O Hashemipour, A Jalali, A Hassanzadeh Analog Integrated Circuits and Signal Processing 86, 327-339, 2016 | 30 | 2016 |
