| Monte Carlo bounding techniques for determining solution quality in stochastic programs WK Mak, DP Morton, RK Wood Operations research letters 24 (1-2), 47-56, 1999 | 891 | 1999 |
| Systems and methods for designing and making integrated circuits with consideration of wiring demand ratio FY Chang, SH Chen, TC Chen, RS Tsay, WK Mak US Patent 8,407,647, 2013 | 92 | 2013 |
| Voltage island generation under performance requirement for SoC designs WK Mak, JW Chen 2007 Asia and South Pacific Design Automation Conference, 798-803, 2007 | 86 | 2007 |
| FOARS: FLUTE based obstacle-avoiding rectilinear Steiner tree construction G Ajwani, C Chu, WK Mak Proceedings of the 19th international symposium on Physical design, 27-34, 2010 | 81 | 2010 |
| Power-driven flip-flop merging and relocation SH Wang, YY Liang, TY Kuo, WK Mak Proceedings of the 2011 international symposium on Physical design, 107-114, 2011 | 72 | 2011 |
| Fast fixed-outline 3-D IC floorplanning with TSV co-placement CR Li, WK Mak, TC Wang IEEE transactions on very large scale integration (VLSI) systems 21 (3), 523-532, 2012 | 54 | 2012 |
| Pin accessibility-driven detailed placement refinement Y Ding, C Chu, WK Mak Proceedings of the 2017 ACM on International Symposium on Physical Design …, 2017 | 52 | 2017 |
| Power minimization algorithms for LUT-based FPGA technology mapping H Li, S Katkoori, WK Mak ACM Transactions on Design Automation of Electronic Systems (TODAES) 9 (1 …, 2004 | 44 | 2004 |
| Throughput optimization for SADP and e-beam based manufacturing of 1D layout Y Ding, C Chu, WK Mak Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 43 | 2014 |
| Temporal logic replication for dynamically reconfigurable FPGA partitioning WK Mak, EFY Young Proceedings of the 2002 international symposium on Physical design, 190-195, 2002 | 42 | 2002 |
| A fast hypergraph min-cut algorithm for circuit partitioning WK Mak, DF Wong Integration 30 (1), 1-11, 2000 | 39 | 2000 |
| On optimal board-level routing for FPGA-based logic emulation WK Mak, DF Wong Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1997 | 38 | 1997 |
| Board-level multiterminal net routing for FPGA-based logic emulation WK Mak, DF Wong ACM Transactions on Design Automation of Electronic Systems (TODAES) 2 (2 …, 1997 | 34 | 1997 |
| LUT-based FPGA technology mapping for power minimization with optimal depth H Li, WK Mak, S Katkoori Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging …, 2001 | 30 | 2001 |
| SafeChoice: A novel approach to hypergraph clustering for wirelength-driven placement JZ Yan, C Chu, WK Mak IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 29 | 2011 |
| Minimum replication min-cut partitioning WK Mak, DF Wong IEEE transactions on computer-aided design of integrated circuits and …, 1997 | 29 | 1997 |
| Mixed-cell-height standard cell placement legalization CY Hung, PY Chou, WK Mak Proceedings of the on Great Lakes Symposium on VLSI 2017, 149-154, 2017 | 28 | 2017 |
| ALMmap: Technology mapping for FPGAs with adaptive logic modules YY Liang, TY Kuo, SH Wang, WK Mak IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 27 | 2012 |
| Efficient LUT-based FPGA technology mapping for power minimization H Li, WK Mak, S Katkoori Proceedings of the 2003 Asia and South Pacific Design Automation Conference …, 2003 | 26 | 2003 |
| Dilation-5 embedding of 3-dimensional grids into hypercubes MY Chan, F Chin, CN Chu, WK Mak Journal of Parallel and Distributed Computing 33 (1), 98-106, 1996 | 23 | 1996 |
