| A 348-μW 68.8-dB SNDR 20-MS/s pipelined SAR ADC with a closed-loop two-stage dynamic amplifier Y Kwon, T Kim, N Sun, Y Chae IEEE Solid-State Circuits Letters 4, 166-169, 2021 | 19 | 2021 |
| A 65-dB-SNDR pipelined SAR ADC Using PVT-robust capacitively degenerated dynamic amplifier H Yoon, C Lee, T Kim, Y Kwon, Y Chae IEEE Journal of Solid-State Circuits 58 (4), 961-971, 2023 | 15 | 2023 |
| A 6b 1.2 GS/s 47.8 mW 0.17 mm2 65 nm CMOS ADC for High-Rate WPAN Systems HL Park, YG Kwon, MH Choi, YL Kim, SH Lee, YD Jeon, JK Kwon JSTS: Journal of Semiconductor Technology and Science 11 (2), 95-103, 2011 | 6 | 2011 |
| A 6b 1.4GS/s 11.9mW 0.11mm2 65nm CMOS DAC with a 2-D INL bounded switching scheme YG Kwon, SH Lee, YD Jeon, JK Kwon 2010 International SoC Design Conference, 198-200, 2010 | 6 | 2010 |
| A 10b 120MS/s 45nm CMOS ADC using a re-configurable three-stage switched Op-amp YJ Kim, KH Lee, SH Ji, YG Kwon, SH Lee, KJ Moon, M Choi, HJ Park, ... IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 5 | 2010 |
| A 50 MS/s 65 dB-SNDR pipelined SAR ADC using capacitively degenerated two-stage dynamic amplifier H Yoon, T Kim, Y Kwon, Y Chae 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 4 | 2022 |
| An 8.1 ENOB 10bit 400MS/s Pipelined ADC Using SAR and Sub-Ranging Flash Y Kwon, B Min, J Lee, W Lee, S Yang 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | 4 | 2021 |
| An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue Amplifier Y Kwon, S Lee, C Lee, H Yoon, B Min, Y Chae 2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2023 | 3 | 2023 |
| A circuit-shared double-channel low-power 10 b 170 MS/s 0.18/m CMOS ADC SM Myung, YG Kwon, SP Nam, HJ Kim, SH Lee Proc. ITC-CSCC, 279-282, 2011 | 1 | 2011 |
| A 0.31 pJ/conv-step 13b 100MS/s 0.13 um CMOS ADC for 3G Communication Systems DS Lee, MH Lee, YG Kwon, SH Lee Journal of the Institute of Electronics Engineers of Korea SD 46 (3), 75-85, 2009 | 1 | 2009 |
