Compact model of subvolume MTJ and its design application at nanoscale technology nodes Y Zhang, B Yan, W Kang, Y Cheng, JO Klein, Y Zhang, Y Chen, W Zhao IEEE Transactions on Electron Devices 62 (6), 2048-2055, 2015 | 106 | 2015 |
A radiation hardened hybrid spintronic/CMOS nonvolatile unit using magnetic tunnel junctions W Zhao, E Deng, JO Klein, Y Cheng, D Ravelosona, Y Zhang, C Chappert Journal of Physics D: Applied Physics 47 (40), 405003, 2014 | 78 | 2014 |
Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs Y Cheng, L Zhang, Y Han, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (2), 239-249, 2012 | 75 | 2012 |
Architecture design with STT-RAM: Opportunities and challenges P Chi, S Li, Y Cheng, Y Lu, SH Kang, Y Xie 2016 21st Asia and South Pacific design automation conference (ASP-DAC), 109-114, 2016 | 72 | 2016 |
Temperature impact analysis and access reliability enhancement for 1T1MTJ STT-RAM B Wu, Y Cheng, J Yang, A Todri-Sanial, W Zhao IEEE Transactions on Reliability 65 (4), 1755-1768, 2016 | 51 | 2016 |
Radiation-induced soft error analysis of STT-MRAM: A device to circuit approach J Yang, P Wang, Y Zhang, Y Cheng, W Zhao, Y Chen, HH Li IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 39 | 2015 |
A survey of test and reliability solutions for magnetic random access memories P Girard, Y Cheng, A Virazel, W Zhao, R Bishnoi, MB Tahoori Proceedings of the IEEE 109 (2), 149-169, 2020 | 38 | 2020 |
Building energy-efficient multi-level cell STT-RAM caches with data compression L Liu, P Chi, S Li, Y Cheng, Y Xie 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 751-756, 2017 | 26 | 2017 |
An adaptive 3T-3MTJ memory cell design for STT-MRAM-based LLCs L Xue, B Wu, B Zhang, Y Cheng, P Wang, C Park, J Kan, SH Kang, Y Xie IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (3), 484-495, 2018 | 21 | 2018 |
Carbon nanotube SRAM in 5-nm technology node design, optimization, and performance evaluation—part I: CNFET transistor optimization R Chen, L Chen, J Liang, Y Cheng, S Elloumi, J Lee, K Xu, VP Georgiev, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (4), 432-439, 2022 | 18 | 2022 |
STT-RAM buffer design for precision-tunable general-purpose neural network accelerator L Song, Y Wang, Y Han, H Li, Y Cheng, X Li IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (4 …, 2017 | 18 | 2017 |
Quantitative evaluation of reliability and performance for STT-MRAM L Zhang, A Todri-Sanial, W Kang, Y Zhang, L Torres, Y Cheng, W Zhao 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1150-1153, 2016 | 18 | 2016 |
Reliability and performance evaluation for STT-MRAM under temperature variation L Zhang, Y Cheng, W Kang, Y Zhang, L Torres, W Zhao, A Todri-Sanial 2016 17th International Conference on Thermal, Mechanical and Multi-Physics …, 2016 | 17 | 2016 |
A body-biasing of readout circuit for STT-RAM with improved thermal reliability L Yang, Y Cheng, Y Wang, H Yu, W Zhao, A Todri-Sanial 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1530-1533, 2015 | 15 | 2015 |
HARS: a high-performance reliable routing scheme for 3D NoCs J Zhou, H Li, Y Fang, T Wang, Y Cheng, X Li 2014 IEEE Computer Society Annual Symposium on VLSI, 392-397, 2014 | 15 | 2014 |
Wrapper chain design for testing TSVs minimization in circuit-partitioned 3D SoC Y Cheng, L Zhang, Y Han, J Liu, X Li 2011 Asian test symposium, 181-186, 2011 | 15 | 2011 |
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective Y Cheng, X Guo, VF Pavlidis Integration 85, 97-107, 2022 | 14 | 2022 |
Variability study of MWCNT local interconnects considering defects and contact resistances—Part I: Pristine MWCNT R Chen, J Liang, J Lee, VP Georgiev, R Ramos, H Okuno, D Kalita, ... IEEE Transactions on Electron Devices 65 (11), 4955-4962, 2018 | 14 | 2018 |
ODESY: A novel 3T-3MTJ cell design with optimized area density, scalability and latency L Xue, Y Cheng, J Yang, P Wang, Y Xie 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 14 | 2016 |
An adaptive thermal-aware ECC scheme for reliable STT-MRAM LLC design B Wu, B Zhang, Y Cheng, Y Wang, D Liu, W Zhao IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (8 …, 2019 | 13 | 2019 |