| 16.6 A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs D Yang, A Abidi, H Darabi, H Xu, D Murphy, H Wu, Z Wang 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 266-268, 2019 | 22 | 2019 |
| An FBAR Driven− 261dB FOM Fractional-N PLL D Yang, D Murphy, H Darabi, A Behzad, R Ruby, R Parker 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 147-150, 2021 | 13 | 2021 |
| A harmonic-mixing PLL architecture for millimeter-wave application D Yang, D Murphy, H Darabi, A Behzad, AA Abidi, SC Au, SR Mundlapudi, ... IEEE Journal of Solid-State Circuits 57 (12), 3552-3566, 2022 | 10 | 2022 |
| A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with− 250dB FoM D Yang, D Murphy, H Darabi, A Behzad, A Abidi, S Au, S Mundlapudi, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 384-386, 2022 | 8 | 2022 |
| A distance-immune low-power 4-Mbps inductively-coupled bidirectional data link A Yousefi, D Yang, AA Abidi, D Markovic 2017 Symposium on VLSI Circuits, C60-C61, 2017 | 8 | 2017 |
| A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise D Murphy, D Yang, H Darabi, A Behzad IEEE Journal of Solid-State Circuits 58 (9), 2513-2525, 2023 | 3 | 2023 |
| A multi-loop calibration-free phase-locked loop (PLL) for wideband clock generation D Yang University of California, Los Angeles, 2019 | 2 | 2019 |
| Jitter, Phase Noise and Spurs in Frequency Multiplying Delay-locked loops: A Simple Model and Analysis D Yang University of California, Los Angeles, 2015 | 2 | 2015 |
| Fbar-based local oscillator generation Hooman Darabi, David Murphy, Arya Behzad, Dihang YANG, Hung-Ming Chien ... US Patent US20200162084A1, 2020 | | 2020 |
| Jitter, Phase Noise and Spurs in Frequency Multiplying Delay-locked loops: A Simple D Yang | | 2015 |
| Amkor Technology, Portugal A Cardoso, A Gouvea, S Nogueira, RT Yazicigil, AA Enabling, ... | | |
