| Tunnelling-based ternary metal–oxide–semiconductor technology JW Jeong, YE Choi, WS Kim, JH Park, S Kim, S Shin, K Lee, J Chang, ... Nature Electronics 2 (7), 307-312, 2019 | 108 | 2019 |
| A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits S Kim, SY Lee, S Park, KR Kim, S Kang IEEE Transactions on Circuits and Systems I: Regular Papers, 2020 | 107 | 2020 |
| Ternary full adder using multi-threshold voltage graphene barristors S Heo, S Kim, K Kim, H Lee, SY Kim, YJ Kim, SM Kim, HI Lee, S Lee, ... IEEE Electron Device Letters 39 (12), 1948-1951, 2018 | 54 | 2018 |
| An optimal gate design for the synthesis of ternary logic circuits S Kim, T Lim, S Kang 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 476-481, 2018 | 52 | 2018 |
| A novel ternary multiplier based on ternary CMOS compact model Y Kang, J Kim, S Kim, S Shin, ES Jang, JW Jeong, KR Kim, S Kang 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), 25-30, 2017 | 38 | 2017 |
| Low-power ternary multiplication using approximate computing S Kim, Y Kang, S Baek, Y Choi, S Kang IEEE Transactions on Circuits and Systems II: Express Briefs 68 (8), 2947-2951, 2021 | 20 | 2021 |
| Demonstration of anti-ambipolar switch and its applications for extremely low power ternary logic circuits Y Lee, S Kim, HI Lee, SM Kim, SY Kim, K Kim, H Kwon, HW Lee, ... Acs Nano 16 (7), 10994-11003, 2022 | 19 | 2022 |
| Ternary logic synthesis with modified Quine-McCluskey algorithm SY Lee, S Kim, S Kang 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 158-163, 2019 | 17 | 2019 |
| Design and analysis of a low-power ternary SRAM Y Choi, S Kim, K Lee, S Kang 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2021 | 14 | 2021 |
| Design of quad-edge-triggered sequential logic circuits for ternary logic S Kim, SY Lee, S Park, S Kang 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 37-42, 2019 | 13 | 2019 |
| Optimizing ternary multiplier design with fast ternary adder J Yoon, S Baek, S Kim, S Kang IEEE Transactions on Circuits and Systems II: Express Briefs 70 (2), 766-770, 2022 | 10 | 2022 |
| Extreme low power technology using ternary arithmetic logic circuits via drastic interconnect length reduction K Kim, S Kim, Y Lee, D Kim, SY Kim, S Kang, BH Lee 2020 IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL), 155-158, 2020 | 8 | 2020 |
| Design and evaluation frameworks for advanced risc-based ternary processor D Kam, JG Min, J Yoon, S Kim, S Kang, Y Lee 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022 | 6 | 2022 |
| Junctionless Negative‐Differential‐Resistance Device Using 2D Van‐Der‐Waals Layered Materials for Ternary Parallel Computing T Lee, KS Jung, S Seo, J Lee, J Park, S Kang, J Park, J Kang, H Ahn, ... Advanced Materials 36 (24), 2310015, 2024 | 2 | 2024 |
| Ternary logic circuit device S Kang, KIM Sunmean, LEE SungYun, P Sunghye US Patent 11,533,054, 2022 | 1 | 2022 |
| Low-power 4-Trit current-steering DAC for ternary data conversion Y Choi, S Kim, S Baek, S Kang 2020 International SoC Design Conference (ISOCC), 254-255, 2020 | 1 | 2020 |
| MTCMOS-based Ternary to Binary Converter S Baek, S Kim, Y Choi, S Kang 2020 International SoC Design Conference (ISOCC), 5-6, 2020 | 1 | 2020 |
| Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU S Park, S Kim, S Kang 2019 International SoC Design Conference (ISOCC), 25-26, 2019 | 1 | 2019 |
| A novel design methodology for error-resilient circuits in near-threshold computing J Lee, S Kim, Y Kim, S Kang 2016 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), 1-4, 2016 | 1 | 2016 |
| Configurable anti-ambipolar photoresponses for optoelectronic multi-valued logic gates X Cui, S Kim, F Ahmed, M Du, AC Liapis, JA Muñoz, AM Shafi, MG Uddin, ... Applied Physics Letters 125 (5), 2024 | | 2024 |
Seokhyeong KangPohang University of Science and Technology (POSTECH)在 postech.ac.kr 的电子邮件经过验证
