| Design of Low Power High-Speed SAR ADC-A Review PS Devitha, A George 2019 3rd International Conference on Computing Methodologies and …, 2019 | 8 | 2019 |
| FPGA implementation of EEG feature extraction and seizure detection S Raj, A George International Journal of Innovative Research in Science, Engineering and …, 2016 | 6 | 2016 |
| Hardware-Efficient DWT Architecture for Image Processing in Visual Sensors Networks J George, Anuja, E.P IEEE Sensors Journal 23 (5), 5382-5390, 2023 | 4 | 2023 |
| Design and implementation of hardware-efficient architecture for saturation-based image dehazing algorithm A George, EP Jayakumar Journal of Real-Time Image Processing 20 (5), 102, 2023 | 2 | 2023 |
| A Novel Design of Low Power, High-Speed SAMM and its FPGA Implementation A George International Journal of Computer Applications 43 (4), 6-9, 2012 | 2 | 2012 |
| Speedy Convolution Using Reversible Vedic Multiplier A George, S Raj International Journal of Scientific and Research Publications 6 (9), 286-291, 2016 | | 2016 |
| Design and validation of SHA 384 IP core C James, N R, A George International Journal of Computer Science & Technology 5 (3), 31-34, 2014 | | 2014 |
| A Novel IEEE 754 Standard Floating-Point Unit Comprising Fused Add-Subtract Unit R C.J, A George, A V IJAREEIE 2 (1), 568-575, 2013 | | 2013 |
| Communications and Instrumentation© 2011 by IJCA Journal Number 2-Article 1 Year of Publication: 2011 A George, N Thankachan, A Harapanahalli | | 2011 |
| A Novel Low Power Design of SRAM cell and its Performance Analysis A George, N Thankachan, A Harapanahalli Proceedings published by International Journal of Computer Applications®, 20-25, 2011 | | 2011 |
Jayakumar E.PNational Institute of Technology Calicut在 nitc.ac.in 的电子邮件经过验证
Jayakumar E.PNational Institute of Technology Calicut在 nitc.ac.in 的电子邮件经过验证