| Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs M De Marchi, D Sacchetto, S Frache, J Zhang, PE Gaillardon, Y Leblebici, ... 2012 International Electron Devices Meeting, 8.4. 1-8.4. 4, 2012 | 323 | 2012 |
| Configurable logic gates using polarity-controlled silicon nanowire gate-all-around FETs M De Marchi, J Zhang, S Frache, D Sacchetto, PE Gaillardon, Y Leblebici, ... IEEE Electron Device Letters 35 (8), 880-882, 2014 | 125 | 2014 |
| Top–down fabrication of gate-all-around vertically stacked silicon nanowire FETs with controllable polarity M De Marchi, D Sacchetto, J Zhang, S Frache, PE Gaillardon, Y Leblebici, ... IEEE transactions on Nanotechnology 13 (6), 1029-1038, 2014 | 109 | 2014 |
| Polarity-controllable silicon nanowire transistors with dual threshold voltages J Zhang, M De Marchi, D Sacchetto, PE Gaillardon, Y Leblebici, ... IEEE Transactions on Electron Devices 61 (11), 3654-3660, 2014 | 86 | 2014 |
| A Schottky-barrier silicon FinFET with 6.0 mV/dec subthreshold slope over 5 decades of current J Zhang, M De Marchi, PE Gaillardon, G De Micheli 2014 IEEE International Electron Devices Meeting, 13.4. 1-13.4. 4, 2014 | 74 | 2014 |
| Nanowire systems: Technology and design PE Gaillardon, LG Amarù, S Bobba, M De Marchi, D Sacchetto, ... Philosophical Transactions of the Royal Society A: Mathematical, Physical …, 2014 | 39 | 2014 |
| Ambipolar silicon nanowire field effect transistor G De Micheli, Y Leblebici, M De Marchi, D Sacchetto US Patent 9,252,252, 2016 | 36 | 2016 |
| Vertically-stacked double-gate nanowire FETs with controllable polarity: From devices to regular ASICs PE Gaillardon, LG Amarù, S Bobba, M De Marchi, D Sacchetto, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 625-630, 2013 | 35 | 2013 |
| Physical synthesis onto a sea-of-tiles with double-gate silicon nanowire transistors S Bobba, M De Marchi, Y Leblebici, G De Micheli Proceedings of the 49th Annual Design Automation Conference, 42-47, 2012 | 35 | 2012 |
| Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors S Bobba, PE Gaillardon, J Zhang, M De Marchi, D Sacchetto, Y Leblebici, ... Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale …, 2012 | 19 | 2012 |
| FPGA design with double-gate carbon nanotube transistors MHB Jamaa, PE Gaillardon, S Frégonèse, M De Marchi, G De Micheli, ... ECS Transactions 34 (1), 1005, 2011 | 16 | 2011 |
| Co-design of ReRAM passive crossbar arrays integrated in 180 nm CMOS technology J Sandrini, M Barlas, M Thammasack, T Demirci, M De Marchi, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6 (3 …, 2016 | 15 | 2016 |
| Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications M De Marchi, MHB Jamaa, G De Micheli 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 65-70, 2010 | 15 | 2010 |
| Proc J Zhang, M De Marchi, PE Gaillardon, G De Micheli Workshop of AAAI Conf. Artificial Intell</i>. AAAI Press, 2014 | 14 | 2014 |
| Spike-based dynamic computing with asynchronous sensing-computing neuromorphic chip M Yao, O Richter, G Zhao, N Qiao, Y Xing, D Wang, T Hu, W Fang, ... Nature Communications 15 (1), 4464, 2024 | 9 | 2024 |
| Towards structured ASICs using polarity-tunable Si nanowire transistors PE Gaillardon, M De Marchi, L Amarù, S Bobba, D Sacchetto, Y Leblebici, ... Proceedings of the 50th Annual Design Automation Conference, 1-4, 2013 | 8 | 2013 |
| Speck: A smart event-based vision sensor with a low latency 327k neuron convolutional neuronal network processing pipeline O Richter, Y Xing, M De Marchi, C Nielsen, M Katsimpris, R Cattaneo, ... | 6 | 2024 |
| Synthesis of regular computational fabrics with ambipolar CNTFET technology M De Marchi, S Bobba, MHB Jamaa, G De Micheli 2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010 | 6 | 2010 |
| Polarity control at runtime: From circuit concept to device fabrication M De Marchi EPFL, 2015 | 5 | 2015 |
| Towards functionality-enhanced devices: Controlling the modes of operation in three-independent-gate transistors PE Gaillardon, J Zhang, M De Marchi, G De Micheli 2015 IEEE Nanotechnology Materials and Devices Conference (NMDC), 1-2, 2015 | 4 | 2015 |
Pierre - Emmanuel GAILLARDONAssociate Professor, University of Utah在 utah.edu 的电子邮件经过验证
