| Performance enhancement of novel InAs/Si hetero double-gate tunnel FET using Gaussian doping S Ahish, D Sharma, YBN Kumar, MH Vasantha IEEE Transactions on Electron Devices 63 (1), 288-295, 2015 | 150 | 2015 |
| Device and circuit level performance analysis of novel InAs/Si heterojunction double gate tunnel field effect transistor S Ahish, D Sharma, MH Vasantha, YBN Kumar Superlattices and Microstructures 94, 119-130, 2016 | 20 | 2016 |
| Design of high performance Multiply-Accumulate Computation unit S Ahish, YBN Kumar, D Sharma, MH Vasantha 2015 IEEE International Advance Computing Conference (IACC), 915-918, 2015 | 14 | 2015 |
| Design and analysis of novel InSb/Si Heterojunction double gate tunnel field effect transistor S Ahish, D Sharma, MH Vasantha, YBN Kumar 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 105-109, 2016 | 13 | 2016 |
| Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor S Ahish, D Sharma, MH Vasantha, YBN Kumar Superlattices and Microstructures 103, 93-101, 2017 | 11 | 2017 |
| DC and analogue/radio frequency performance optimisation of heterojunction double‐gate tunnel field‐effect transistor S Ahish, D Sharma, YB Nithin Kumar, MH Vasantha Micro & Nano Letters 11 (8), 407-411, 2016 | 4 | 2016 |
| Effect of Drain Doping and Temperature Variation on the Performance of Heterojunction Double Gate Tunnel Field Effect Transistor from a 2D ATLAS Simulation S Ahish, D Sharma, YBN Kumar, MH Vasantha Journal of Nanoelectronics and Optoelectronics 12 (2), 162-170, 2017 | 2 | 2017 |
| Implementation of double-gate junctionless transistor and its circuit performance analysis RK Joshi, TV Arjun, S Ahish, D Sharma, MH Vasantha, YBN Kumar 2016 IEEE Students’ Technology Symposium (TechSym), 278-283, 2016 | 1 | 2016 |
| Performance analysis of a novel hetero-junction tunnel FET based SRAM at 0.3 V supply voltage MKZ Ansari, S Ahish, D Sharma, MH Vasantha, YBN Kumar 2016 IEEE Students’ Technology Symposium (TechSym), 224-228, 2016 | 1 | 2016 |
