| A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation D Cherniak, L Grimaldi, L Bertulessi, R Nonis, C Samori, S Levantino IEEE Journal of Solid-State Circuits, 2018 | 86 | 2018 |
| A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation D Cherniak, L Grimaldi, L Bertulessi, C Samori, R Nonis, S Levantino Solid-State Circuits Conference-(ISSCC), 2018 IEEE International, 248-250, 2018 | 86 | 2018 |
| A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking SL Alessio Santiccioli, Mario Mercandelli, Luca Bertulessi, Angelo Parisi ... IEEE Journal of Solid-State Circuits 55 (12), 3349 - 3361, 2020 | 84 | 2020 |
| 17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking A Santiccioli, M Mercandelli, L Bertulessi, A Parisi, D Cherniak, AL Lacaita, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 268-270, 2020 | 84 | 2020 |
| A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter M Mercandelli, A Santiccioli, A Parisi, L Bertulessi, D Cherniak, AL Lacaita, ... IEEE Journal of Solid-State Circuits 57 (2), 505-517, 2021 | 71 | 2021 |
| A Background Calibration Technique to Control the Bandwidth of Digital PLLs M Mercandelli, L Grimaldi, L Bertulessi, C Samori, AL Lacaita, ... IEEE Journal of Solid-State Circuits 53 (11), 3243-3255, 2018 | 52 | 2018 |
| A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range L Bertulessi, L Grimaldi, D Cherniak, C Samori, S Levantino 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 252-254, 2018 | 41 | 2018 |
| 16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS L Grimaldi, L Bertulessi, S Karman, D Cherniak, A Garghetti, C Samori, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 268-270, 2019 | 32 | 2019 |
| A 30-GHz Digital Sub-Sampling Fractional- PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS L Bertulessi, S Karman, D Cherniak, A Garghetti, C Samori, AL Lacaita, ... IEEE Journal of Solid-State Circuits 54 (12), 3493-3502, 2019 | 26 | 2019 |
| A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 20 | 2022 |
| A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping SM Dartizio, F Tesolin, M Mercandelli, A Santiccioli, A Shehata, S Karman, ... IEEE Journal of Solid-State Circuits 57 (6), 1723-1735, 2021 | 15 | 2021 |
| 32.3 A 12.9-to-15.1 GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping achieving 107.6 fs integrated jitter M Mercandelli, A Santiccioli, SM Dartizio, A Shehata, F Tesolin, S Karman, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 445-447, 2021 | 15 | 2021 |
| 4.3 A 76.7 fs-lntegrated-Jitter and− 71.9 dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering SM Dartizio, F Tesolin, G Castoro, F Buccoleri, L Lanzoni, M Rossoni, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 3-5, 2023 | 14 | 2023 |
| A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking … SM Dartizio, F Buccoleri, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... IEEE Journal of Solid-State Circuits 57 (12), 3538-3551, 2022 | 12 | 2022 |
| 4.5 A 9.25 GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology G Castoro, SM Dartizio, F Tesolin, F Buccoleri, M Rossoni, D Cherniak, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 82-84, 2023 | 11 | 2023 |
| 32.8 A 98.4 fs-Jitter 12.9-to-15.1 GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays A Santiccioli, M Mercandelli, SM Dartizio, F Tesolin, S Karman, A Shehata, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 456-458, 2021 | 10 | 2021 |
| A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations G Bè, A Parisi, L Bertulessi, L Ricci, L Scaletti, M Mercandelli, AL Lacaita, ... IEEE Transactions on Circuits and Systems II: Express Briefs 69 (9), 3645-3649, 2022 | 7 | 2022 |
| Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise L Bertulessi, D Cherniak, M Mercandelli, C Samori, AL Lacaita, ... IEEE Transactions on Circuits and Systems I: Regular Papers 69 (5), 1858-1870, 2022 | 7 | 2022 |
| A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... 2022 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2022 | 5 | 2022 |
| A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner F Buccoleri, SM Dartizio, F Tesolin, L Avallone, A Santiccioli, A Iesurum, ... IEEE Journal of Solid-State Circuits 58 (3), 634-646, 2022 | 4 | 2022 |
Salvatore LevantinoPolitecnico di Milano在 polimi.it 的电子邮件经过验证
