| Design of reconfigurable LFSR for VLSI IC testing in ASIC and FPGA KN Devika, R Bhakthavatchalu 2017 international conference on communication and signal processing (ICCSP …, 2017 | 47 | 2017 |
| Reseeding LFSR for test pattern generation PS Dilip, GR Somanathan, R Bhakthavatchalu 2019 International Conference on Communication and Signal Processing (ICCSP …, 2019 | 32 | 2019 |
| UVM based testbench architecture for logic sub-system verification TM Pavithran, R Bhakthavatchalu 2017 International Conference on Technological Advancements in Power and …, 2017 | 31 | 2017 |
| A comparison of pipelined parallel and iterative CORDIC design on FPGA R Bhakthavatchalu, MS Sinith, P Nair, K Jismi 2010 5th International Conference on Industrial and Information Systems, 239-243, 2010 | 29 | 2010 |
| Parameterizable FPGA implementation of SHA-256 using blockchain concept KN Devika, R Bhakthavatchalu 2019 International conference on communication and signal processing (ICCSP …, 2019 | 27 | 2019 |
| Deterministic seed selection and pattern reduction in Logic BIST R Bhakthavatchalu, S Krishnan, V Vineeth, MN Devi 18th International Symposium on VLSI Design and Test, 1-2, 2014 | 25 | 2014 |
| FPGA based delay PUF implementation for security applications MA Kumar, R Bhakthavatchalu 2017 International Conference on Technological Advancements in Power and …, 2017 | 18 | 2017 |
| Programmable MISR modules for logic BIST based VLSI testing KN Devika, R Bhakthavatchalu 2016 International Conference on Control, Instrumentation, Communication and …, 2016 | 18 | 2016 |
| Design of optimized CIC decimator and interpolator in FPGA R Bhakthavatchalu, VS Karthika, L Ramesh, B Aamani 2013 International Mutli-Conference on Automation, Computing, Communication …, 2013 | 17 | 2013 |
| Modified FPGA based design and implementation of reconfigurable FFT architecture R Bhakthavatchalu, A Kripalal, S Nair, P Venugopal, M Viswanath 2013 International Mutli-Conference on Automation, Computing, Communication …, 2013 | 13 | 2013 |
| Comparative study of test pattern generation systems to reduce test application time PS Dilip, GR Somanathan, R Bhakthavatchalu 2019 9th International Symposium on Embedded Computing and System Design …, 2019 | 12 | 2019 |
| Design of efficient programmable test-per-scan logic BIST modules KN Devika, R Bhakthavatchalu 2017 International conference on Microelectronic Devices, Circuits and …, 2017 | 12 | 2017 |
| Time of flight measurement system for an ultrasonic anemometer P Chandran, R Bhakthavatchalu, PP Kumar 2016 International Conference on Control, Instrumentation, Communication and …, 2016 | 12 | 2016 |
| Verilog design of programmable JTAG controller for digital VLSI IC’s R Bhakthavatchalu, SK Kannan, MN Devi Indian Journal of Science and Technology 8 (17), 1-7, 2015 | 12 | 2015 |
| Design and Analysis of Test Pattern Generator by combining internal and external LFSR CS Vikranth, K Rakesh, B Jagadeesh, D Mohammad, GR Somanathan, ... 2021 5th International Conference on Trends in Electronics and Informatics …, 2021 | 11 | 2021 |
| 32-bit reconfigurable logic-BIST design using Verilog for ASIC chips R Bhakthavatchalu, GR Deepthy, SS Mallia, R HariKrishnan, A Krishnan, ... 2011 IEEE Recent Advances in Intelligent Computational Systems, 386-390, 2011 | 11 | 2011 |
| Low latency max log MAP based turbo decoder A Narayanan, S Murugan, R Bhakthavatchalu 2019 International Conference on Communication and Signal Processing (ICCSP …, 2019 | 9 | 2019 |
| Implementation of re-configurable open core protocol compliant memory system using VHDL R Bhakthavatchalu, GR Deepthy, S Shanooja 2010 5th International Conference on Industrial and Information Systems, 213-218, 2010 | 9 | 2010 |
| Design and implementation of Izhikevich, Hodgkin and Huxley spiking neuron models and their comparison J Kumar, J Kumar, S Murali, R Bhakthavatchalu 2016 International Conference on Advanced Communication Control and …, 2016 | 8 | 2016 |
| Comparison of reconfigurable FFT processor implementation using CORDIC and multipliers R Bhakthavatchalu, NA Kareem, J Arya 2011 IEEE Recent Advances in Intelligent Computational Systems, 343-347, 2011 | 8 | 2011 |
Geethu Remadevi SomanathanAmrita Vishwa Vidyapeetham, Amritapuri在 am.amrita.edu 的电子邮件经过验证
