| A machine learning approach for optimization of channel geometry and source/drain doping profile of stacked nanosheet transistors H Xu, W Gan, L Cao, C Yang, J Wu, M Zhou, H Qu, S Zhang, H Yin, Z Wu IEEE Transactions on Electron Devices 69 (7), 3568-3574, 2022 | 18 | 2022 |
| Layout optimization of complementary FET 6T-SRAM cell based on a universal methodology using sensitivity with respect to parasitic-and-values Y Luo, L Cao, Q Zhang, Y Cao, Z Zhang, J Yao, G Yan, X Zhang, W Gan, ... IEEE Transactions on Electron Devices 69 (11), 6095-6101, 2022 | 12 | 2022 |
| Novel channel-first fishbone FETs with symmetrical threshold voltages and balanced driving currents using single work function metal process L Cao, Q Zhang, Y Luo, J Gu, W Gan, P Lu, J Yao, H Xu, P Zhao, K Luo, ... IEEE Transactions on Electron Devices 69 (11), 5971-5977, 2022 | 10 | 2022 |
| Investigation of novel hybrid channel complementary FET scaling beyond 3-nm node from device to circuit Y Luo, Q Zhang, L Cao, W Gan, H Xu, Y Cao, J Gu, R Xu, G Yan, J Huo, ... IEEE Transactions on Electron Devices 69 (7), 3581-3588, 2022 | 10 | 2022 |
| Geometric variability aware quantum potential based quasi-ballistic compact model for stacked 6 nm-thick silicon nanosheet GAA-FETs S Huang, Z Wu, H Xu, J Guo, L Xu, XL Duan, Q Chen, G Yang, Q Zhang, ... 2021 IEEE International Electron Devices Meeting (IEDM), 18.5. 1-18.5. 4, 2021 | 8 | 2021 |
| Stacked HZO/α-In2Se3 Ferroelectric Dielectric/Semiconductor FET With Ultrahigh Speed and Large Memory Window J Huo, Z Zhang, Y Zhang, F Zhang, G Yan, G Tian, H Xu, G Zhan, G Xu, ... IEEE Transactions on Electron Devices 70 (6), 3071-3075, 2023 | 4 | 2023 |
| Physical insights of Si-core-SiGe-shell gate-all-around nanosheet pFET for 3 nm technology node H Xu, J Yao, Z Yang, L Cao, Q Zhang, Y Li, A Du, H Yin, Z Wu IEEE Transactions on Electron Devices 70 (6), 3365-3371, 2023 | 4 | 2023 |
| Overview of emerging semiconductor device model methodologies: From device physics to machine learning engines X Li, Z Wu, G Rzepa, M Karner, H Xu, Z Wu, W Wang, G Yang, Q Luo, ... Fundamental Research, 2024 | 3 | 2024 |
| Bottom Dielectric Isolation to Suppress Sub-Fin Parasitic Channel of Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices L Cao, Y Liu, Z Wu, Q Zhang, J Yao, Y Luo, H Xu, P Zhao, K Luo, Y Wu, ... 2022 China Semiconductor Technology International Conference (CSTIC), 1-3, 2022 | 3 | 2022 |
| Investigation on dependency of thermal characteristics on gate/drain bias voltages in stacked nanosheet transistors P Zhao, L Cao, F Zhang, H Xu, W Gan, Q Zhang, Z Zhang, J Yao, G Tian, ... Microelectronics Journal 141, 105970, 2023 | 2 | 2023 |
| Vertically Stacked Nanosheet Number Optimization Strategy for Complementary FET (CFET) Scaling Beyond 2 nm S Li, Y Luo, H Xu, J Huo, Z Di, Y Li, Q Zhang, H Yin, Z Wu IEEE Transactions on Electron Devices, 2023 | 1 | 2023 |
| Prediction of key metrics of stacked nanosheet nfets using genetic algorithm-based neural networks H Xu, W Gan, L Cao, H Yin, Z Wu 2022 IEEE International Conference on Integrated Circuits, Technologies and …, 2022 | 1 | 2022 |
| CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology HH Radamson, Y Miao, Z Zhou, Z Wu, Z Kong, J Gao, H Yang, Y Ren, ... Nanomaterials 14 (10), 837, 2024 | | 2024 |
| Virtual FAB Semiconductor Process Modeling Augmented Vertical Gate All Around Complementary FET Based 6T SRAM Path-Finding Z Di, Y Luo, H Xu, H He, H Yin, Z Wu 2024 Conference of Science and Technology for Integrated Circuits (CSTIC), 1-3, 2024 | | 2024 |
| Nanosheet Count Optimization Strategy of Complementary FET (CFET) Scaling Beyond 2 nm From Device to Circuit H He, S Li, Y Luo, H Xu, H Yin, Z Wu 2023 International Workshop on Advanced Patterning Solutions (IWAPS), 1-4, 2023 | | 2023 |
| Machine Learning-augmented High-efficient TCAD on Accurate Characteristics of Gate-all-around Transistors with Quantum Effect H Xu, G Zhan, S Li, J Wu, K Luo, Y Liu, C He, Z Wu 2023 International Conference on Simulation of Semiconductor Processes and …, 2023 | | 2023 |
| Investigation of Synergic Hydrogen Mitigation Technique for Top-Gate A-IGZO Thin-Film Transistors G Yan, Z Song, H Xu, S Yang, C Niu, G Tian, Y Luo, L Zhang, Y Bao, G Xu, ... 2023 China Semiconductor Technology International Conference (CSTIC), 1-3, 2023 | | 2023 |
| Device-Circuit Co-Optimization for Negative Capacitance FinFETs based on SPICE Model J Huo, W Huang, F Zhang, Q Huo, W Gan, H Xu, H Zhu, H Yin, Z Wu 2020 International Workshop on Advanced Patterning Solutions (IWAPS), 1-4, 2020 | | 2020 |
| A Physical Modeling Study of Mobility Enhancement in Stressed Ge-on-insulator pMOSFET H Xu, G Wang, J Yao, H Yin, H Radamson, Z Wu 2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2019 | | 2019 |
| Kaikai Wu, Hongyi Wang, Shucai Wang H Xu, W Gan, L Cao, H Yin, Z Wu, N Ran, J Li, S Ma, Y Yang, W Zhao, ... | | |
