| Logic locking for IP security: A comprehensive analysis on challenges, techniques, and trends J Gandhi, D Shekhawat, M Santosh, JG Pandey Computers & Security 129, 103196, 2023 | 7 | 2023 |
| Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher K Jhawar, J Gandhi, D Shekhawat, A Upadhyay, A Harkishanka, ... Journal of Real-Time Image Processing 21 (2), 32, 2024 | 1 | 2024 |
| LOKI: a secure FPGA Prototyping of IoT IP with lightweight logic locking J Gandhi, D Shekhawat, M Santosh, JG Pandey 2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 85-89, 2023 | 1 | 2023 |
| A time domain 2D OaA-based convolutional neural networks accelerator RP Singh, S Kumar, J Gandhi, D Shekhawat, M Santosh, JG Pandey Memories-Materials, Devices, Circuits and Systems 4, 100041, 2023 | 1 | 2023 |
| GAN4IP: A unified GAN and logic locking-based pipeline for hardware IP security J Gandhi, D Shekhawat, M Santosh, JG Pandey Sādhanā 49 (2), 169, 2024 | | 2024 |
| SAT and SCOPE Attacks on Deceptive Multiplexer Logic Locking J Gandhi, R Agarwal, A Mall, D Shekhawat, M Santosh, JG Pandey 2024 37th International Conference on VLSI Design and 2024 23rd …, 2024 | | 2024 |
| Security Evaluation of Lightweight SBoxes J Gandhi, D Shekhawat, M Santosh, JG Pandey 2023 IEEE International Symposium on Smart Electronic Systems (iSES), 315-318, 2023 | | 2023 |
| PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations D Shekhawat, J Gandhi, M Santosh, JG Pandey Conference on Next Generation Arithmetic, 88-100, 2023 | | 2023 |
| PHAc: Posit Hardware Accelerator for Efficient Arithmetic Operations D Shekhawat | | |
Diksha ShekhawatAcademy of Scientific and Innovative Research, CSIR-CEERI, Pilani在 ceeri.res.in 的电子邮件经过验证
