| Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor NI Deligiannis, R Cantoro, T Faller, T Paxian, B Becker, MS Reorda 2021 IEEE 30th Asian Test Symposium (ATS), 73-78, 2021 | 11 | 2021 |
| Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network R Cantoro, NI Deligiannis, MS Reorda, M Traiola, E Valea 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2020 | 10 | 2020 |
| Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks NI Deligiannis, R Cantoro, MS Reorda, M Traiola, E Valea IEEE Access 9, 155998-156012, 2021 | 9 | 2021 |
| New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core NI Deligiannis, R Cantoro, M Sauer, B Becker, MS Reorda 2021 IEEE 39th VLSI Test Symposium (VTS), 1-7, 2021 | 7 | 2021 |
| Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques NI Deligiannis, R Cantoro, MS Reorda Microprocessors and Microsystems 98, 104775, 2023 | 6 | 2023 |
| Constraint-based automatic SBST generation for RISC-V processor families T Faller, NI Deligiannis, M Schwörer, MS Reorda, B Becker 2023 IEEE European Test Symposium (ETS), 1-6, 2023 | 5 | 2023 |
| Automating the generation of programs maximizing the repeatable constant switching activity in microprocessor units via MaxSAT NI Deligiannis, T Faller, R Cantoro, T Paxian, B Becker, MS Reorda IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2023 | 5 | 2023 |
| Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques NI Deligiannis, R Cantoro, MS Reorda 2021 24th Euromicro Conference on Digital System Design (DSD), 535-540, 2021 | 5 | 2021 |
| A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors J Anders, P Andreu, B Becker, S Becker, R Cantoro, NI Deligiannis, ... 2023 IEEE European Test Symposium (ETS), 1-10, 2023 | 3 | 2023 |
| Evaluating the Code Encryption Effects on Memory Fault Resilience R Cantoro, NI Deligiannis, MS Reorda, M Traiola, E Valea 2020 IEEE Latin-American Test Symposium (LATS), 1-6, 2020 | 2 | 2020 |
| Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing NI Deligiannis, T Faller, Z Chenghan, R Cantoro, B Becker, MS Reorda 2023 IEEE European Test Symposium (ETS), 1-5, 2023 | 1 | 2023 |
| Using Formal Methods to Support the Development of STLs for GPUs NI Deligiannis, T Faller, JER Condia, R Cantoro, B Becker, MS Reorda 2022 IEEE 31st Asian Test Symposium (ATS), 84-89, 2022 | 1 | 2022 |
| Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms NI Deligiannis, R Cantoro, MS Reorda, M Traiola, E Valea 2022 52nd Annual IEEE/IFIP International Conference on Dependable Systems …, 2022 | 1 | 2022 |
| Fault Grading Techniques for Evaluating Software-Based Self-Test with Respect to Small Delay Defects M Bartolomucci, N Deligiannis, R Cantoro, MS Reorda Proceedings of The 30th IEEE International Symposium on On-Line Testing and …, 2024 | | 2024 |
| Evaluating the Reliability of Integer Multipliers With Respect to Permanent Faults NI Deligiannis, R Cantoro, MS Reorda, SED Habib 2024 27th International Symposium on Design & Diagnostics of Electronic …, 2024 | | 2024 |
| Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors NI Deligiannis, T Faller, I Guglielminetti, R Cantoro, B Becker, MS Reorda 2023 IEEE 32nd Asian Test Symposium (ATS), 1-6, 2023 | | 2023 |
| Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters R Esteban, N Deligiannis, J Sini, R Cantoro, M SONZA REORDA Proceedings of ISC High Performance 2023, 2023 | | 2023 |
| A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors A Jens, A Pablo, B Bernd, B Steffen, R Cantoro, N Deligiannis, E Nourhan, ... Proceedings of European Test Symposium 2023, 2023 | | 2023 |
| Constraint-Based Automatic SBST Generation for RISC-V Processor Families T Faller, NI Deligiannis, M Schwörer, MS Reorda, B Becker 2023 IEEE European Test Symposium (ETS), 1-6, 2023 | | 2023 |
| Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters JER Condia, NI Deligiannis, J Sini, R Cantoro, MS Reorda International Conference on High Performance Computing, 444-457, 2023 | | 2023 |
Matteo SONZA REORDAPolitecnico di Torino, Dept. of Control and Computer Engineering在 polito.it 的电子邮件经过验证
