| A 6.94-fJ/conversion-step 12-bit 100-MS/s asynchronous SAR ADC exploiting split-CDAC in 65-nm CMOS M Li, Y Yao, B Hu, J Wei, Y Chen, S Ma, F Ye, J Ren IEEE Access 9, 77545-77554, 2021 | 20 | 2021 |
| A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting M Li, CY Lee, PK Venkatachala, A ElShater, Y Miyahara, K Sobue, ... IEEE Journal of Solid-State Circuits, 2023 | 18 | 2023 |
| A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC M Li, Y Chen, F Ye, J Ren 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2018 | 5 | 2018 |
| A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers Y Yao, J Wei, M Li, S Ma, F Ye, J Ren 2019 IEEE 13th International Conference on ASIC (ASICON), 1-4, 2019 | 2 | 2019 |
| A stacked-packaged 16-channel ADC for ultrasound application Y Wu, Y Chen, M Li, F Ye, J Ren 2017 IEEE 12th International Conference on ASIC (ASICON), 245-248, 2017 | 2 | 2017 |
| A 12bit asynchronous SAR-incremental sub-range ADC M Li, H Hu, Z Dai, F Ye, J Ren 2017 IEEE 12th International Conference on ASIC (ASICON), 835-838, 2017 | 1 | 2017 |
| A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation H Hu, M Li, Z Dai, F Ye, J Ren 2017 IEEE 12th International Conference on ASIC (ASICON), 686-689, 2017 | 1 | 2017 |
| A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique H Hu, Z Dai, M Li, F Ye, J Ren 2017 IEEE 12th International Conference on ASIC (ASICON), 179-182, 2017 | 1 | 2017 |
| An Easy-to-Drive Discrete-Time ADC Topology Using Digital Predictive Level-Shifting M Li, R Gao, C Wilson, A Basak, EC Markwell, ML Johnston, UK Moon 2024 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2024 | | 2024 |
| A 16-Bit 100kHz Bandwidth Pseudo-Pseudo-Differential Delta-Sigma ADC M Li, CY Lee, H Wang, GC Temes, UK Moon 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | | 2023 |
| 10.4 A Rail-to-Rail 12MS 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting M Li, CY Lee, A ElShater, Y Miyahara, K Sobue, K Tomioka, UK Moon 2023 IEEE International Solid-State Circuits Conference (ISSCC) 66 (10.4 …, 2023 | | 2023 |
| SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors Y Yao, M Li, T Wu, H Xu, S Ma, W Bao, J Ren 2019 IEEE 13th International Conference on ASIC (ASICON), 1-4, 2019 | | 2019 |
| A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC Z Dai, H Hu, M Li, F Ye, J Ren 2017 IEEE 12th International Conference on ASIC (ASICON), 28-31, 2017 | | 2017 |
