| Exploration and development of tri-gate quantum well barrier FinFET with strained nanosystem channel for enhanced performance S Nanda, RS Dhar Computers & Electrical Engineering 98, 107687, 2022 | 8 | 2022 |
| Implementation and Characterization of 14 nm Trigate HOI n-FinFET using Strained Silicon channel with reduced area on chip S Nanda, RS Dhar 2021 6th International Conference for Convergence in Technology (I2CT), 1-4, 2021 | 7 | 2021 |
| Effects of dimensional variations on short channel parameters in 14 nm channel length TG–SOI FinFETs P Saha, S Nanda, P Yugender, RS Dhar Advances in Communication, Devices and Networking: Proceedings of ICCDN 2021 …, 2022 | 5 | 2022 |
| Development and analysis of a three-fin trigate Q-FinFET for a 3 nm technology node with a strained-silicon channel system S Nanda, RS Dhar, F Awwad, MI Hussein Nanomaterials 13 (10), 1662, 2023 | 4 | 2023 |
| Comparative performance analysis based short channel effects for TG Nano FinFETs Z Renthlei, RS Dhar, S Nanda Journal of Physics: Conference Series 1921 (1), 012014, 2021 | 4 | 2021 |
| The optimization and analysis of a triple-fin heterostructure-on-insulator fin field-effect transistor with a stacked high-K configuration and 10 nm channel length P Saha, R Sankar Dhar, S Nanda, K Kumar, M Alathbah Nanomaterials 13 (23), 3008, 2023 | 3 | 2023 |
| Impact of High-k Dielectric Materials on Short Channel Effects in Tri-gate SOI FinFETs Z Renthlei, S Nanda, RS Dhar Journal of Nano-and Electronic Physics 13 (5), 2021 | 3 | 2021 |
| Modelling and Implementation of Double Gate n-channel FET with Strain Engineered Tri-Layered Channel System for Enriched Drain Current K Kumar, R Sankar Dhar, S Nanda Journal of Nano- and Electronic Physics 14 (2), 02028-1 - 02028-5, 2022 | 2 | 2022 |
| Parametric analysis for varied gate work function in trigate n-channel FinFET A Srivastava, S Nanda, SE Aimol, RS Dhar 2021 Devices for Integrated Circuit (DevIC), 359-362, 2021 | 2 | 2021 |
| Low Power Nine-bit Sigma-Delta ADC Design using TSMC 0.18 micron Technology SS Biswal, S Nanda, P Kabisatpathy International Journal of Technology Exploration and Learning (IJTEL) 2 (5 …, 2013 | 2 | 2013 |
| Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system S Nanda, RS Dhar Physica Scripta 99 (4), 045932, 2024 | 1 | 2024 |
| Performance parameter analysis and estimation of high-K induced three-fin SOI n-FinFET at 14 nm gate length RS Dhar, SK Sinha, A Verma, T Chowdhury, HS Tomar, S Nanda, ... International Journal of Nanoparticles 14 (2-4), 226-237, 2022 | 1 | 2022 |
| Effect of High-k Dielectric Materials on Short Channel Effects of a 14 nm Tri-Gate SOI FinFET for Reduced Area on Chip S Nanda, RS Dhar Journal of Nano- and Electronic Physics 13 (03), 03015-1 - 03015-4, 2021 | 1 | 2021 |
| Exploration and analysis of n-FinFET implementing stacked high-K at 08 nm gate length S Nanda, S Kumari, RS Dhar Sādhanā 49 (1), 11, 2023 | | 2023 |
| Design and Performance Analysis of 3-Fin 08 nm Physical Gate Length SOI FinFETs Employing Gate Stacked High-K Dielectrics S Nanda, S Kumari, RS Dhar 2023 IEEE 3rd International Conference on Applied Electromagnetics, Signal …, 2023 | | 2023 |
| Exploration of effects of gate underlap in HOI FinFETs at 10 nm gate length P Datta, S Nanda, RS Dhar Physica Scripta 98 (7), 074003, 2023 | | 2023 |
| Development and Analysis of a Three-Fin Trigate Q-FinFET for a 3 nm Technology Node with a Strained-Silicon Channel System. Nanomaterials 2023, 13, 1662 S Nanda, RS Dhar, F Awwad, MI Hussein | | 2023 |
| Improvement Analysis of Leakage Currents with Stacked High-k/Metal Gate in 10 nm Strained Channel HOI FinFET P Kumari, S Nanda, P Saha, RS Dhar Journal of Nano-and Electronic Physics 14 (2), 02004-1 - 02004-4, 2022 | | 2022 |
| Geometrical Optimization of 10 nm Channeled TG–HOI FinFET using tri-layered Strained Silicon Channel S Nanda, RS Dhar 2021 International Conference on Intelligent Technologies (CONIT), 1-4, 2021 | | 2021 |
| Performance Estimation and Analysis of 3D Trigate HOI FinFET Using Strained Channel for Reduced Area S Nanda, RS Dhar Innovations in Electrical and Electronic Engineering: Proceedings of ICEEE …, 2021 | | 2021 |
