| Heterogeneous 2.5 D integration on through silicon interposer X Zhang, JK Lin, S Wickramanayaka, S Zhang, R Weerasekera, R Dutta, ... Applied physics reviews 2 (2), 2015 | 166 | 2015 |
| A blockchain-based approach using smart contracts to develop a smart waste management system Y Sen Gupta, S Mukherjee, R Dutta, S Bhattacharya International Journal of Environmental Science and Technology, 1-24, 2022 | 48 | 2022 |
| Physics informed neural network using finite difference method KL Lim, R Dutta, M Rotaru 2022 IEEE International Conference on Systems, Man, and Cybernetics (SMC …, 2022 | 16 | 2022 |
| Design and development of high density fan-out wafer level package (HD-FOWLP) for deep neural network (DNN) chiplet accelerators using advanced interface bus (AIB) MD Rotaru, W Tang, D Rahul, Z Zhang 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 1258-1263, 2021 | 15 | 2021 |
| An analytical capacitance model for through-silicon vias in floating silicon substrate R Weerasekera, G Katti, R Dutta, S Zhang, KF Chang, J Zhou, ... IEEE Transactions on Electron Devices 63 (3), 1182-1188, 2016 | 11 | 2016 |
| High bandwidth interconnect design opportunities in 2.5 D Through-silicon interposer (TSI) R Weerasekera, KF Chang, S Zhang, G Katti, HY Li, R Dutta, JR Cubillo 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 241-244, 2016 | 10 | 2016 |
| Fabrication and assembly of Cu-RDL-based 2.5-D low-cost through silicon interposer (LC–TSI) G Katti, SW Ho, LH Yu, S Zhang, R Dutta, R Weerasekera, KF Chang, ... IEEE Design & Test 32 (4), 23-31, 2015 | 10 | 2015 |
| Method and system for predicting performance in electronic design based on machine learning R Salahuddin, R Dutta, KTC Chai, A James, CS Foo, Z Zeng, ... US Patent App. 17/296,169, 2022 | 8 | 2022 |
| Co-packaging of PMUT array with FOWLP ASIC's D Giusti, F Quaglia, D Rahul, VS Rao, A Savoia, M Shaw, DHS Wee 2022 IEEE 24th Electronics Packaging Technology Conference (EPTC), 280-285, 2022 | 6 | 2022 |
| Advanced system in package enabled by wafer level heterogeneous integration of chiplets S Bhattacharya, TG Lim, D Ho, KJ Chui, XW Zhang, MD Rotaru, BG Sajay, ... 2022 International Electron Devices Meeting (IEDM), 3.1. 1-3.1. 4, 2022 | 5 | 2022 |
| Automated deep learning platform for accelerated analog circuit design R Dutta, A James, S Raju, YJ Jeon, CS Foo, KTC Chai 2022 IEEE 35th International System-on-Chip Conference (SOCC), 1-5, 2022 | 5 | 2022 |
| NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging T Chou, W Tang, MD Rotaru, C Liu, R Dutta, SLP Siang, DHS Wee, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 5 | 2022 |
| Method and system for generating training data for a machine learning model for predicting performance in electronic design R Dutta, R Salahuddin, KTC Chai US Patent App. 17/296,657, 2022 | 5 | 2022 |
| Bayesian Deep Active Learning for Analog Circuit Performance Classification L Zhang, S Raju, A James, R Dutta, G Fournier, D Lancry, KCT Chuan, ... 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 3018-3022, 2022 | 4 | 2022 |
| Material removal rate prediction using the classification-regression approach KL Lim, R Dutta 2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC), 172-175, 2020 | 4 | 2020 |
| An automatic chip-package co-design flow for multi-core neuromorphic computing SiPs J Lan, VP Nambiar, R Sabapathy, R Dutta, CT Chong, MD Rotaru, KK Lin, ... 2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC), 77-80, 2020 | 3 | 2020 |
| Prognostics and health management of wafer chemical-mechanical polishing system using autoencoder KL Lim, R Dutta 2021 IEEE International Conference on Prognostics and Health Management …, 2021 | 2 | 2021 |
| Automated Design Flow for Millimeter-Wave Antenna in Fan-Out Wafer Level Packaging S Wang, D Rahul, D Xie, LT Guan, F Che, Y Han, S Bhattacharya 2019 IEEE 21st Electronics Packaging Technology Conference (EPTC), 448-451, 2019 | 2 | 2019 |
| Heterogeneous system implementation using through-silicon interposer (TSI) technology R Weerasekera, Z Songbai, R Dutta, G Katti, KF Chang, J Zhou, JK Lin, ... 2015 IEEE International Conference on Electron Devices and Solid-State …, 2015 | 2 | 2015 |
| Applied Physics Reviews C Zhang, F Li, JL Zhu, JG Lu, J Qiang, EW Zhong, ZC Ye, Z He, X Guo, ... Appl. Phys. Lett 141905 (10.1063/1.4915604), 106, 2015 | 2 | 2015 |
