| Transaction-level model simulator for communication-limited accelerators S Kim, J Wang, Y Seo, S Lee, Y Park, S Park, CS Park arXiv preprint arXiv:2007.14897, 2020 | 12 | 2020 |
| Optimization of Communication Schemes for DMA-Controlled Accelerators J Wang, S Park, CS Park IEEE Access, 2021 | 5 | 2021 |
| Design and implementation of a Farrow-interpolator-based digital front-end in LTE receivers for carrier aggregation CS Park, S Kim, J Wang, S Park Electronics 10 (3), 231, 2021 | 5 | 2021 |
| Convolutional neural network accelerator with reconfigurable dataflow M Oh, C Lee, S Lee, Y Seo, S Kim, J Wang, CS Park 2018 International SoC Design Conference (ISOCC), 42-43, 2018 | 4 | 2018 |
| Optimizations of scatter network for sparse CNN accelerators S Kim, C Lee, H Park, J Wang, S Park, CS Park 2019 IEEE International Conference on Artificial Intelligence Circuits and …, 2019 | 3 | 2019 |
| Spatial data dependence graph simulator for convolutional neural network accelerators J Wang, J Kim, S Moon, S Kim, S Park, CS Park 2019 IEEE International Conference on Artificial Intelligence Circuits and …, 2019 | 3 | 2019 |
| Spatial data dependence graph based pre-rtl simulator for convolutional neural network dataflows J Wang, S Park, CS Park IEEE Access 10, 11382-11403, 2022 | 2 | 2022 |
| Latency-insensitive controller for convolutional neural network accelerators Y Seo, S Lee, S Kim, J Wang, S Park, CS Park 2019 International SoC Design Conference (ISOCC), 249-250, 2019 | 2 | 2019 |
| eF2lowSim: System-Level Simulator of eFlash-Based Compute-in-Memory Accelerators for Convolutional Neural Networks J Wang, S Kim, J Heo, CS Park 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 1 | 2023 |
| Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs J Wang, Y Gim, S Park, CS Park IEEE Access 10, 25901-25921, 2022 | | 2022 |
