| 8.7 A 112Gb/s ADC-DSP-based PAM-4 transceiver for long-reach applications with> 40dB channel loss in 7nm FinFET P Mishra, A Tan, B Helal, CR Ho, C Loi, J Riani, J Sun, K Mistry, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 138-140, 2021 | 63 | 2021 |
| A flash-based non-uniform sampling ADC with hybrid quantization enabling digital anti-aliasing filter TF Wu, CR Ho, MSW Chen IEEE Journal of Solid-State Circuits 52 (9), 2335-2349, 2017 | 55 | 2017 |
| A digital PLL with feedforward multi-tone spur cancellation scheme achieving<–73 dBc fractional spur and<–110 dBc reference spur in 65 nm CMOS CR Ho, MSW Chen IEEE Journal of Solid-State Circuits 51 (12), 3216-3230, 2016 | 53 | 2016 |
| A fractional-N DPLL with calibration-free multi-phase injection-locked TDC and adaptive single-tone spur cancellation scheme CR Ho, MSW Chen IEEE Transactions on Circuits and Systems I: Regular Papers 63 (8), 1111-1122, 2016 | 26 | 2016 |
| Adaptive spur cancellation techniques and multi-phase injection locked TDC for digital phase locked loop circuit SW Chen, HO Cheng-Ru US Patent 9,941,891, 2018 | 18 | 2018 |
| A fractional-N digital PLL with background-dither-noise-cancellation loop achieving<-62.5 dBc worst-case near-carrier fractional spurs in 65nm CMOS CR Ho, MSW Chen 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 394-396, 2018 | 17 | 2018 |
| A Fractional-N Digital MDLL With Background Two-Point DTC Calibration Q Zhang, S Su, CR Ho, MSW Chen IEEE Journal of Solid-State Circuits 57 (1), 80-89, 2021 | 16 | 2021 |
| 29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving-60dBc Fractional Spur Q Zhang, S Su, CR Ho, MSW Chen 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 410-412, 2021 | 15 | 2021 |
| A fractional-N DPLL with adaptive spur cancellation and calibration-free injection-locked TDC in 65nm CMOS CR Ho, MSW Chen 2014 IEEE Radio Frequency Integrated Circuits Symposium, 97-100, 2014 | 12 | 2014 |
| A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling CR Ho, MSW Chen 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 254-256, 2018 | 7 | 2018 |
| Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS CR Ho, MSW Chen ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 213-216, 2016 | 7 | 2016 |
| A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS TF Wu, CR Ho, MSW Chen 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015 | 5 | 2015 |
| Smoothing the way for digital phase-locked loops: Clock generation in the future with digital signal processing for mitigating spur and interference CR Ho, MSW Chen IEEE Microwave Magazine 20 (5), 80-97, 2019 | 4 | 2019 |
| 7.1 A 2.69 pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET JQ Wang, A Tan, A Iyer, A Fan, A Farhoodfar, B Alnabulsi, B Smith, C Loi, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 123-125, 2024 | | 2024 |
| ISSCC 2021/SESSION 29/DIGITAL CIRCUITS FOR COMPUTING, CLOCKING AND POWER MANAGEMENT/29.4 Q Zhang, S Su, CR Ho, MSW Chen | | |
