| Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization KK Chang, A Kashyap, H Hassan, S Ghose, K Hsieh, D Lee, T Li, ... Proceedings of the 2016 ACM SIGMETRICS International Conference on …, 2016 | 241 | 2016 |
| Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms KK Chang, AG Yağlıkçı, S Ghose, A Agrawal, N Chatterjee, A Kashyap, ... Proceedings of the ACM on Measurement and Analysis of Computing Systems 1 (1 …, 2017 | 226 | 2017 |
| Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization KK Chang, AG Yaglikci, A Agrawal, N Chatterjee, S Ghose, A Kashyap, ... Analysis, and Mechanisms. In SIGMETRICS 3 (5.5), 3.5, 2017 | 30 | 2017 |
| Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency KK Chang, AG Yaglıkçı, S Ghose, A Agrawal, N Chatterjee, A Kashyap, ... arXiv preprint arXiv:1805.03175, 2018 | 9 | 2018 |
| On chip characterization of timing parameters for memory ports AR Kashyap, S Pundoor US Patent 9,570,195, 2017 | 7 | 2017 |
| Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips KK Chang, A Kashyap, H Hassan, S Ghose, K Hsieh, D Lee, T Li, ... arXiv preprint arXiv:1805.03154, 2018 | 1 | 2018 |
| Mitigating duty cycle distortion degradation due to device aging on high-bandwidth memory interface I Chadha, V Kumar, V Katyal, A Kashyap US Patent 12,027,198, 2024 | | 2024 |
| Digital delay line calibration with duty cycle correction for high bandwidth memory interface I Chadha, V Kumar, A Kashyap, V Katyal, HY Wei US Patent 11,936,379, 2024 | | 2024 |
| Understanding Reduced-Voltage Operation in Modern DRAM Devices KK Chang, O Mutlu, AG Yaăhıkçı, S Ghose, A Agrawal, N Chatterjee, ... Proceedings of the 2017 ACM SIGMETRICS/International Conference on …, 2017 | | 2017 |
| MDLL & Slave Delay Line performance analysis using novel delay modeling A Kashyap, A Shambu, K Shah Design and Verification Conference India, Bangalore, 2014 | | 2014 |
| Improving Timing Closure by optimizing placement of Clock Tree Elements A Kashyap Cadence CDNLive India, 2013 | | 2013 |
| Voltron: Understanding and Exploiting the Voltage–Latency–Reliability Trade-O s in Modern DRAM Chips to Improve Energy E ciency KK Chang, AG Yağlıkçı, S Ghose, A Agrawal, N Chatterjee, A Kashyap, ... | | |
