| A tagless coherence directory J Zebchuk, V Srinivasan, MK Qureshi, A Moshovos Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 201 | 2009 |
| A framework for coarse-grain optimizations in the on-chip memory hierarchy J Zebchuk, E Safi, A Moshovos 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007 | 79 | 2007 |
| Multi-grain coherence directories J Zebchuk, B Falsafi, A Moshovos Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 68 | 2013 |
| Methods of cache preloading on a partition or a context switch HW Cain III, V Srinivasan, J Zebchuk US Patent 9,529,723, 2016 | 36 | 2016 |
| A dual grain hit-miss detector for large die-stacked DRAM caches M El-Nacouzi, I Atta, M Papadopoulou, J Zebchuk, NE Jerger, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 89-92, 2013 | 20 | 2013 |
| Recap: a region-based cure for the common cold cache J Zebchuk, HW Cain, V Shrinivasan, A Moshovos Proceedings of the 21st international conference on Parallel architectures …, 2012 | 16 | 2012 |
| Evaluating the memory system behavior of smartphone workloads G Narancic, P Judd, D Wu, I Atta, M Elnacouzi, J Zebchuk, J Albericio, ... 2014 International Conference on Embedded Computer Systems: Architectures …, 2014 | 13 | 2014 |
| Re-examining cache replacement policies J Zebchuk, S Makineni, D Newell 2008 IEEE International Conference on Computer Design, 671-678, 2008 | 11 | 2008 |
| Regiontracker: A case for dual-grain tracking in the memory system J Zebchuk, A Moshovos Technical report, Computer Group, University of Toronto, 2006 | 6 | 2006 |
| Teaching old caches new tricks: RegionTracker and predictor virtualization I Burcea, J Zebchuk, A Moshovos 2009 IEEE Pacific Rim Conference on Communications, Computers and Signal …, 2009 | 3 | 2009 |
| RegionTracker: Using dual-grain tracking for energy efficient cache lookup J Zebchuk, A Moshovos Workshop on Complexity Effective Design, co-located with the Int’l Symp. on …, 2006 | 3 | 2006 |
| A preliminary exploration of memory controller policies on smartphone workloads G Narancic, M Papadopoulou, J Zebchuk University of Toronto 41, 52, 2012 | 2 | 2012 |
| Methods of cache preloading on a partition or a context switch HW Cain III, V Srinivasan, J Zebchuk US Patent 10,963,387, 2021 | | 2021 |
| Methods of cache preloading on a partition or a context switch HW Cain III, V Srinivasan, J Zebchuk US Patent 10,268,588, 2019 | | 2019 |
| Methods of cache preloading on a partition or a context switch HW Cain III, V Srinivasan, J Zebchuk US Patent 9,804,967, 2017 | | 2017 |
| Reducing the Area and Energy of Coherence Directories in Multicore Processors J Zebchuk | | 2013 |
| A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy J Zebchuk, A Moshovos IEEE Computer Architecture Letters 6 (2), 33-36, 2007 | | 2007 |
| REGIONTR4CKER: A FR4MEWORK FOR COARSE-GRAIN OPTIMZ4TIONS IN THE ON-CHIP MEMORY HIERARCHY J Zebchuk University of Toronto, 2007 | | 2007 |
Andreas MoshovosProfessor, Electrical and Computer Engineering, University of Toronto在 eecg.toronto.edu 的电子邮件经过验证
Andreas MoshovosProfessor, Electrical and Computer Engineering, University of Toronto在 eecg.toronto.edu 的电子邮件经过验证
Moinuddin QureshiProfessor, Georgia Institute of Technology在 gatech.edu 的电子邮件经过验证