| A 20nm 1.8 V 8Gb PRAM with 40MB/s program bandwidth Y Choi, I Song, MH Park, H Chung, S Chang, B Cho, J Kim, Y Oh, D Kwon, ... Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 …, 2012 | 452 | 2012 |
| A multi-functional in-memory inference processor using a standard 6T SRAM array M Kang, SK Gonugondla, A Patil, NR Shanbhag IEEE Journal of Solid-State Circuits 53 (2), 642-655, 2018 | 234 | 2018 |
| A 42pJ/decision 3.12 TOPS/W robust in-memory machine learning classifier with on-chip training SK Gonugondla, M Kang, N Shanbhag 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 490-492, 2018 | 206 | 2018 |
| An energy-efficient VLSI architecture for pattern recognition via deep embedding of computation in SRAM M Kang, MS Keel, NR Shanbhag, S Eilert, K Curewitz 2014 IEEE International Conference on Acoustics, Speech and Signal …, 2014 | 202 | 2014 |
| A variation-tolerant in-memory machine learning classifier via on-chip training SK Gonugondla, M Kang, NR Shanbhag IEEE Journal of Solid-State Circuits 53 (11), 3163-3173, 2018 | 122 | 2018 |
| An in-memory VLSI architecture for convolutional neural networks M Kang, S Lim, S Gonugondla, NR Shanbhag IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (3 …, 2018 | 85 | 2018 |
| 9.1 A 7nm 4-core AI chip with 25.6 TFLOPS hybrid FP8 training, 102.4 TOPS INT4 inference and workload-aware throttling A Agrawal, SK Lee, J Silberman, M Ziegler, M Kang, S Venkataramani, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 144-146, 2021 | 73 | 2021 |
| PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms P Srivastava*, M Kang* (*equal contribution), SK Gonugondla, S Lim, ... International Symposium on Computer Architecture (ISCA18), 2018 | 71 | 2018 |
| RaPiD: AI accelerator for ultra-low precision training and inference S Venkataramani, V Srinivasan, W Wang, S Sen, J Zhang, A Agrawal, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 70 | 2021 |
| A 19.4-nJ/decision, 364-K decisions/s, in-memory random forest multi-class inference accelerator M Kang, SK Gonugondla, S Lim, NR Shanbhag IEEE Journal of Solid-State Circuits 53 (7), 2126-2135, 2018 | 63 | 2018 |
| An MRAM-based deep in-memory architecture for deep neural networks AD Patil, H Hua, S Gonugondla, M Kang, NR Shanbhag 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 54 | 2019 |
| Efficient AI system design with cross-layer approximate computing S Venkataramani, X Sun, N Wang, CY Chen, J Choi, M Kang, A Agarwal, ... Proceedings of the IEEE 108 (12), 2232-2250, 2020 | 51 | 2020 |
| An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks M Kang, SK Gonugondla, MS Keel, NR Shanbhag 2015 IEEE International Conference on Acoustics, Speech and Signal …, 2015 | 49 | 2015 |
| A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array M Kang, SK Gonugondla, NR Shanbhag ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 263-266, 2017 | 47 | 2017 |
| Compute memory N Shanbhag, MG Kang, MS Keel US Patent 9,697,877, 2017 | 47 | 2017 |
| FinFET SRAM optimization with fin thickness and surface orientation M Kang, SC Song, SH Woo, HK Park, MH Abu-Rahma, L Ge, BM Han, ... IEEE Transactions on Electron Devices 57 (11), 2785-2793, 2010 | 42 | 2010 |
| A 3.0 TFLOPS 0.62 V scalable processor core for high compute utilization AI training and inference J Oh, SK Lee, M Kang, M Ziegler, J Silberman, A Agrawal, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 41 | 2020 |
| Energy-efficient and high throughput sparse distributed memory architecture M Kang, EP Kim, M Keel, NR Shanbhag 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2505-2508, 2015 | 40 | 2015 |
| A 481pJ/decision 3.4 M decision/s multifunctional deep in-memory inference processor using standard 6T SRAM array M Kang, S Gonugondla, A Patil, N Shanbhag arXiv preprint arXiv:1610.07501, 2016 | 37 | 2016 |
| In-memory computing architectures for sparse distributed memory M Kang, NR Shanbhag IEEE transactions on biomedical circuits and systems 10 (4), 855-863, 2016 | 36 | 2016 |
